fix minor bug which also frees up r4

This commit is contained in:
2025-07-15 12:53:02 -04:00
parent 4920c3b92b
commit 42ad32b0cc

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@@ -9,22 +9,23 @@ prog:
imm6 0x1
load r0, r2 ; value to increment by
; r1+r2=(r3 & r4)
; r1+r2=r3
add ; add r1 + value
load r3, r4 ; over-write upper MSB to store a copy
load r3, r2 ; store result in r2
imm6 0x32
load r0, r1
sub ; 50 - r2 = remainder
; r3 (C) holds the difference between 50 and our result
imm6 prog.result
beqz ; if r3 == 0 branch to [r0]
load r4, r1
load r2, r1
imm6 prog.loop
ba ; else, copy result to r1 and loop
.result:
out r4
out r2
halt