added memory operation definitions

added halt alias for hcf
This commit is contained in:
2023-07-27 18:21:30 -04:00
parent 43f7481540
commit 683de17be0

View File

@@ -15,13 +15,16 @@
3 => 0b011 3 => 0b011
4 => 0b100 4 => 0b100
5 => 0b101 5 => 0b101
RES => 0b111
} }
#ruledef #ruledef
{ {
imm6 {value} => 0b00 @ value`6 imm6 {value} => 0b00 @ value`6
load r{src: register}, r{dst: register} => 0b10 @ src`3 @ dst`3 load r{src: register}, r{dst: register} => 0b10 @ src`3 @ dst`3
load [r3], r{dst: register} => 0b10 @ 0b110 @ dst`3
load r{src: register}, [r3] => 0b10 @ src`3 @ 0b110
aload => 0b10 @ 0b110 @ 0b110
in r{r: register} => 0b10 @ 0b110 @ r in r{r: register} => 0b10 @ 0b110 @ r
out r{r: register} => 0b10 @ r @ 0b110 out r{r: register} => 0b10 @ r @ 0b110
} }
@@ -36,16 +39,19 @@
sub => 0b01 @ 0b000 @ 0b101 sub => 0b01 @ 0b000 @ 0b101
ALU_RES1 => 0b01 @ 0b000 @ 0b110 ALU_RES1 => 0b01 @ 0b000 @ 0b110
ALU_RES2 => 0b01 @ 0b000 @ 0b111 ALU_RES2 => 0b01 @ 0b000 @ 0b111
ALU_EXT1_RES1 => 0b01 @ 0b001 @ 0b000 ALU_EXT1_RES0 => 0b01 @ 0b001 @ 0b000
ALU_EXT1_RES2 => 0b01 @ 0b001 @ 0b001 ALU_EXT1_RES1 => 0b01 @ 0b001 @ 0b001
ALU_EXT1_RES3 => 0b01 @ 0b001 @ 0b010 ALU_EXT1_RES2 => 0b01 @ 0b001 @ 0b010
ALU_EXT1_RES4 => 0b01 @ 0b001 @ 0b011 ALU_EXT1_RES3 => 0b01 @ 0b001 @ 0b011
ALU_EXT1_RES5 => 0b01 @ 0b001 @ 0b100 ALU_EXT1_RES4 => 0b01 @ 0b001 @ 0b100
ALU_EXT1_RES6 => 0b01 @ 0b001 @ 0b101 ALU_EXT1_RES5 => 0b01 @ 0b001 @ 0b101
ALU_EXT1_RES7 => 0b01 @ 0b001 @ 0b110 ALU_EXT1_RES6 => 0b01 @ 0b001 @ 0b110
ALU_EXT1_RES8 => 0b01 @ 0b001 @ 0b111 ALU_EXT1_RES7 => 0b01 @ 0b001 @ 0b111
; and so on...
ALU_EXT7_RES1 => 0b01 @ 0b111 @ 0b000
} }
; conditional jump block
#ruledef #ruledef
{ {
bn => 0b11 @ 0b000 @ 0b000 bn => 0b11 @ 0b000 @ 0b000
@@ -58,7 +64,9 @@
bgtz => 0b11 @ 0b000 @ 0b111 bgtz => 0b11 @ 0b000 @ 0b111
} }
; halt encodings
#ruledef #ruledef
{ {
hcf => 0b10 @ 0b111 @ 0b111 hcf => 0b10 @ 0b111 @ 0b111
halt => 0b10 @ 0b111 @ 0b111
} }