diff --git a/src/TC_answers/add.asm b/src/microcode/TC_answers/add.asm similarity index 100% rename from src/TC_answers/add.asm rename to src/microcode/TC_answers/add.asm diff --git a/src/TC_answers/laser_canons.asm b/src/microcode/TC_answers/laser_canons.asm similarity index 100% rename from src/TC_answers/laser_canons.asm rename to src/microcode/TC_answers/laser_canons.asm diff --git a/src/TC_answers/masking_time.asm b/src/microcode/TC_answers/masking_time.asm similarity index 100% rename from src/TC_answers/masking_time.asm rename to src/microcode/TC_answers/masking_time.asm diff --git a/src/TC_answers/memory_test.asm b/src/microcode/TC_answers/memory_test.asm similarity index 100% rename from src/TC_answers/memory_test.asm rename to src/microcode/TC_answers/memory_test.asm diff --git a/src/TC_answers/special_invasion.asm b/src/microcode/TC_answers/special_invasion.asm similarity index 100% rename from src/TC_answers/special_invasion.asm rename to src/microcode/TC_answers/special_invasion.asm diff --git a/src/TC_answers/storage_cracker.asm b/src/microcode/TC_answers/storage_cracker.asm similarity index 100% rename from src/TC_answers/storage_cracker.asm rename to src/microcode/TC_answers/storage_cracker.asm diff --git a/src/TC_answers/the_maze.asm b/src/microcode/TC_answers/the_maze.asm similarity index 100% rename from src/TC_answers/the_maze.asm rename to src/microcode/TC_answers/the_maze.asm diff --git a/src/definitions.asm b/src/microcode/definitions.asm similarity index 94% rename from src/definitions.asm rename to src/microcode/definitions.asm index bee9668..3213c21 100644 --- a/src/definitions.asm +++ b/src/microcode/definitions.asm @@ -37,7 +37,6 @@ 3 => 0b011 4 => 0b100 5 => 0b101 - } ; immediate load encodings @@ -51,8 +50,8 @@ { load r{src: register}, r{dst: register} => 0b10 @ src`3 @ dst`3 aload => 0b10 @ 0b110 @ 0b110 - in r{r: register} => 0b10 @ 0b110 @ r - out r{r: register} => 0b10 @ r @ 0b110 + in r{r: register} => 0b10 @ 0b110 @ r`3 + out r{r: register} => 0b10 @ r`3 @ 0b110 } ; EXT0 functions diff --git a/src/misc/50count.asm b/src/microcode/misc/50count.asm similarity index 100% rename from src/misc/50count.asm rename to src/microcode/misc/50count.asm diff --git a/src/microcode/misc/outport_test.asm b/src/microcode/misc/outport_test.asm new file mode 100644 index 0000000..acdaf98 --- /dev/null +++ b/src/microcode/misc/outport_test.asm @@ -0,0 +1,8 @@ +#include "../definitions.asm" +#bank program + +prog: + imm6 42 +.result: + out r0 + halt \ No newline at end of file diff --git a/src/scratch.asm b/src/scratch.asm index c7d1496..db0caf9 100644 --- a/src/scratch.asm +++ b/src/scratch.asm @@ -1,8 +1,6 @@ #include "definitions.asm" -; just a quick scratch pad place for programs +; template/scratch pad prog: - in r1 - in r2 - xor + imm6 0x1 .result: - out r3 \ No newline at end of file + out r0 diff --git a/src/verilog/ECP8_components/ALU.v b/src/verilog/ECP8_components/ALU.v new file mode 100644 index 0000000..6eec289 --- /dev/null +++ b/src/verilog/ECP8_components/ALU.v @@ -0,0 +1,221 @@ +module ALU (clk, rst, Instruction, A, B, D_OUT_EN, D, CF, C); + parameter UUID = 0; + parameter NAME = ""; + input wire clk; + input wire rst; + + input wire [7:0] Instruction; + input wire [7:0] A; + input wire [7:0] B; + output wire [0:0] D_OUT_EN; + output wire [7:0] D; + output wire [0:0] CF; + output wire [7:0] C; + + TC_Splitter8 # (.UUID(64'd1753460274403159300 ^ UUID)) Splitter8_0 (.in(wire_29), .out0(wire_7), .out1(wire_82), .out2(wire_55), .out3(wire_69), .out4(wire_42), .out5(wire_31), .out6(), .out7()); + TC_Decoder3 # (.UUID(64'd812012822489249482 ^ UUID)) Decoder3_1 (.dis(1'd0), .sel0(wire_7), .sel1(wire_82), .sel2(wire_55), .out0(wire_5), .out1(wire_1), .out2(wire_4), .out3(wire_16), .out4(wire_24), .out5(wire_0), .out6(wire_26), .out7(wire_48)); + TC_Add # (.UUID(64'd1656672475853897358 ^ UUID), .BIT_WIDTH(64'd8)) Add8_2 (.in0(wire_86), .in1(wire_45), .ci(1'd0), .out(wire_33), .co(wire_21)); + TC_Switch # (.UUID(64'd2854607076807969927 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_3 (.en(wire_24), .in(wire_2), .out(wire_72)); + TC_Switch # (.UUID(64'd1098925891083976806 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_4 (.en(wire_24), .in(wire_6), .out(wire_84)); + TC_Switch # (.UUID(64'd272865694635219578 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_5 (.en(wire_24), .in(wire_62), .out(wire_22_4)); + TC_Neg # (.UUID(64'd4234413084985973774 ^ UUID), .BIT_WIDTH(64'd8)) Neg8_6 (.in(wire_68), .out(wire_45)); + TC_Add # (.UUID(64'd2365866274018282956 ^ UUID), .BIT_WIDTH(64'd8)) Add8_7 (.in0(wire_84), .in1(wire_72), .ci(1'd0), .out(wire_62), .co(wire_23)); + TC_Switch # (.UUID(64'd2540442194520213284 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_8 (.en(wire_16), .in(wire_6), .out(wire_86)); + TC_Switch # (.UUID(64'd927777902762540353 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_9 (.en(wire_16), .in(wire_2), .out(wire_68)); + TC_Switch # (.UUID(64'd4324181735425917878 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_10 (.en(wire_16), .in(wire_33), .out(wire_22_2)); + TC_Switch # (.UUID(64'd1224106639434152846 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_11 (.en(wire_5), .in(wire_6), .out(wire_39)); + TC_Switch # (.UUID(64'd1322051027298697595 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_12 (.en(wire_5), .in(wire_2), .out(wire_60)); + TC_Switch # (.UUID(64'd4279546958457643910 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_13 (.en(wire_5), .in(wire_52), .out(wire_8_0)); + TC_Switch # (.UUID(64'd1407183183188242545 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_14 (.en(wire_1), .in(wire_2), .out(wire_66)); + TC_Switch # (.UUID(64'd825188955478831971 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_15 (.en(wire_1), .in(wire_6), .out(wire_34)); + TC_Switch # (.UUID(64'd51925339328697175 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_16 (.en(wire_1), .in(wire_27), .out(wire_8_1)); + TC_Switch # (.UUID(64'd1175792227051955560 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_17 (.en(wire_4), .in(wire_6), .out(wire_37)); + TC_Switch # (.UUID(64'd1768630870230821680 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_18 (.en(wire_4), .in(wire_2), .out(wire_73)); + TC_Switch # (.UUID(64'd724522933239860619 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_19 (.en(wire_4), .in(wire_14), .out(wire_8_2)); + TC_Switch # (.UUID(64'd480414198129629098 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_20 (.en(wire_16), .in(wire_2), .out(wire_41)); + TC_Switch # (.UUID(64'd2236984552964180078 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_21 (.en(wire_16), .in(wire_6), .out(wire_71)); + TC_Switch # (.UUID(64'd2331894452996132707 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_22 (.en(wire_16), .in(wire_36), .out(wire_8_3)); + TC_And # (.UUID(64'd4486090735793310582 ^ UUID), .BIT_WIDTH(64'd8)) And8_23 (.in0(wire_71), .in1(wire_41), .out(wire_36)); + TC_Nor # (.UUID(64'd428177551435513699 ^ UUID), .BIT_WIDTH(64'd8)) Nor8_24 (.in0(wire_37), .in1(wire_73), .out(wire_14)); + TC_Or # (.UUID(64'd1391410677810137682 ^ UUID), .BIT_WIDTH(64'd8)) Or8_25 (.in0(wire_39), .in1(wire_60), .out(wire_52)); + TC_Nand # (.UUID(64'd4025048423625330072 ^ UUID), .BIT_WIDTH(64'd8)) Nand8_26 (.in0(wire_34), .in1(wire_66), .out(wire_27)); + TC_Decoder3 # (.UUID(64'd3807680616509469728 ^ UUID)) Decoder3_27 (.dis(1'd0), .sel0(wire_69), .sel1(wire_42), .sel2(wire_31), .out0(wire_25), .out1(wire_30), .out2(wire_20), .out3(wire_75), .out4(wire_74), .out5(wire_46), .out6(wire_61), .out7(wire_70)); + TC_Xnor # (.UUID(64'd4268350311478768457 ^ UUID), .BIT_WIDTH(64'd8)) Xnor8_28 (.in0(wire_49), .in1(wire_81), .out(wire_59)); + TC_Xor # (.UUID(64'd4527214351160864442 ^ UUID), .BIT_WIDTH(64'd8)) Xor8_29 (.in0(wire_64), .in1(wire_12), .out(wire_40)); + TC_Not # (.UUID(64'd3618579806912338026 ^ UUID), .BIT_WIDTH(64'd8)) Not8_30 (.in(wire_58), .out(wire_63)); + TC_Mul # (.UUID(64'd86800450212264749 ^ UUID), .BIT_WIDTH(64'd8)) Mul8_31 (.in0(wire_51), .in1(wire_56), .out0(wire_80), .out1(wire_65)); + TC_Ashr # (.UUID(64'd4224934934216498493 ^ UUID), .BIT_WIDTH(64'd8)) Ashr8_32 (.in(wire_19), .shift(wire_53), .out(wire_43)); + TC_Neg # (.UUID(64'd687800544475925346 ^ UUID), .BIT_WIDTH(64'd8)) Neg8_33 (.in(wire_11), .out(wire_67)); + TC_Rol # (.UUID(64'd1317775489477211882 ^ UUID), .BIT_WIDTH(64'd8)) Rol8_34 (.in(wire_47), .shift(wire_9), .out(wire_3)); + TC_Ror # (.UUID(64'd703554170280240747 ^ UUID), .BIT_WIDTH(64'd8)) Ror8_35 (.in(wire_76), .shift(wire_54), .out(wire_18)); + TC_Shr # (.UUID(64'd3748108855456900138 ^ UUID), .BIT_WIDTH(64'd8)) Shr8_36 (.in(wire_17), .shift(wire_50), .out(wire_38)); + TC_Shl # (.UUID(64'd2176974598361832761 ^ UUID), .BIT_WIDTH(64'd8)) Shl8_37 (.in(wire_85), .shift(wire_57), .out(wire_83)); + TC_Switch # (.UUID(64'd4483630066362025873 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_38 (.en(wire_0), .in(wire_2), .out(wire_12)); + TC_Switch # (.UUID(64'd3908274583674926227 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_39 (.en(wire_0), .in(wire_6), .out(wire_64)); + TC_Switch # (.UUID(64'd4553681126267151464 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_40 (.en(wire_0), .in(wire_40), .out(wire_8_5)); + TC_Switch # (.UUID(64'd4186982137889621636 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_41 (.en(wire_24), .in(wire_2), .out(wire_81)); + TC_Switch # (.UUID(64'd1386256187545231870 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_42 (.en(wire_24), .in(wire_6), .out(wire_49)); + TC_Switch # (.UUID(64'd2659168137376368183 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_43 (.en(wire_24), .in(wire_59), .out(wire_8_4)); + TC_Switch # (.UUID(64'd1704066470517955937 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_44 (.en(wire_26), .in(wire_6), .out(wire_58)); + TC_Switch # (.UUID(64'd2990116238052745508 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_45 (.en(wire_26), .in(wire_63), .out(wire_8_6)); + TC_Switch # (.UUID(64'd2820576902535906486 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_46 (.en(wire_5), .in(wire_2), .out(wire_53)); + TC_Switch # (.UUID(64'd59631099816967048 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_47 (.en(wire_5), .in(wire_6), .out(wire_19)); + TC_Switch # (.UUID(64'd3451848842388615139 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_48 (.en(wire_5), .in(wire_43), .out(wire_22_3)); + TC_Switch # (.UUID(64'd4081918304701245721 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_49 (.en(wire_24), .in(wire_6), .out(wire_11)); + TC_Switch # (.UUID(64'd918819339348151073 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_50 (.en(wire_24), .in(wire_67), .out(wire_15_3)); + TC_Switch # (.UUID(64'd2919540118461118324 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_51 (.en(wire_1), .in(wire_6), .out(wire_79)); + TC_Switch # (.UUID(64'd3749247787192934141 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_52 (.en(wire_4), .in(wire_2), .out(wire_56)); + TC_Switch # (.UUID(64'd2395464300934186678 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_53 (.en(wire_4), .in(wire_6), .out(wire_51)); + TC_Switch # (.UUID(64'd1468357425860970596 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_54 (.en(wire_1), .in(wire_10), .out(wire_22_0)); + TC_Switch # (.UUID(64'd3788856213916320068 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_55 (.en(wire_1), .in(wire_78), .out(wire_44_0)); + TC_Switch # (.UUID(64'd3734865121253732914 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_56 (.en(wire_4), .in(wire_80), .out(wire_22_1)); + TC_Switch # (.UUID(64'd3847724417649658373 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_57 (.en(wire_4), .in(wire_65), .out(wire_44_1)); + TC_Switch # (.UUID(64'd2706629240204870554 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_58 (.en(wire_5), .in(wire_2), .out(wire_9)); + TC_Switch # (.UUID(64'd2001149239728006462 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_59 (.en(wire_5), .in(wire_6), .out(wire_47)); + TC_Switch # (.UUID(64'd2870113753177518410 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_60 (.en(wire_1), .in(wire_2), .out(wire_54)); + TC_Switch # (.UUID(64'd340004962580308093 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_61 (.en(wire_1), .in(wire_6), .out(wire_76)); + TC_Switch # (.UUID(64'd1684711578759063957 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_62 (.en(wire_4), .in(wire_6), .out(wire_17)); + TC_Switch # (.UUID(64'd2389968685784586327 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_63 (.en(wire_16), .in(wire_2), .out(wire_57)); + TC_Switch # (.UUID(64'd4535804765991235387 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_64 (.en(wire_16), .in(wire_6), .out(wire_85)); + TC_Switch # (.UUID(64'd667890680105453361 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_65 (.en(wire_4), .in(wire_2), .out(wire_50)); + TC_Switch # (.UUID(64'd3924371852208470488 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_66 (.en(wire_1), .in(wire_18), .out(wire_15_2)); + TC_Switch # (.UUID(64'd4550216520043673402 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_67 (.en(wire_5), .in(wire_3), .out(wire_15_4)); + TC_Switch # (.UUID(64'd1040267906917435020 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_68 (.en(wire_4), .in(wire_38), .out(wire_15_0)); + TC_Switch # (.UUID(64'd1068858050083309300 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_69 (.en(wire_16), .in(wire_83), .out(wire_15_1)); + TC_Switch # (.UUID(64'd1056292847970768806 ^ UUID), .BIT_WIDTH(64'd1)) Switch1_70 (.en(wire_24), .in(wire_23), .out(wire_13_0)); + TC_Switch # (.UUID(64'd2775044829367273609 ^ UUID), .BIT_WIDTH(64'd1)) Switch1_71 (.en(wire_16), .in(wire_21), .out(wire_13_1)); + TC_Switch # (.UUID(64'd683797453120618047 ^ UUID), .BIT_WIDTH(64'd8)) Output8z_72 (.en(wire_35), .in(wire_44), .out(D)); + TC_Switch # (.UUID(64'd1344327710761016922 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_73 (.en(wire_25), .in(wire_8), .out(wire_32_2)); + TC_Switch # (.UUID(64'd3164243025886628350 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_74 (.en(wire_30), .in(wire_22), .out(wire_32_1)); + TC_Switch # (.UUID(64'd389001382807605908 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_75 (.en(wire_20), .in(wire_15), .out(wire_32_0)); + TC_Or # (.UUID(64'd2298387723272408160 ^ UUID), .BIT_WIDTH(64'd1)) Or_76 (.in0(wire_1), .in1(wire_4), .out(wire_28)); + TC_And # (.UUID(64'd4016989336483643045 ^ UUID), .BIT_WIDTH(64'd1)) And_77 (.in0(wire_28), .in1(wire_30), .out(wire_35)); + TC_Mul # (.UUID(64'd3859724630390996553 ^ UUID), .BIT_WIDTH(64'd8)) DivMod8_78 (.in0(wire_79), .in1(wire_77), .out0(wire_10), .out1(wire_78)); + TC_Switch # (.UUID(64'd2129354784258529228 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_79 (.en(wire_1), .in(wire_2), .out()); + TC_Constant # (.UUID(64'd1325873776756270234 ^ UUID), .BIT_WIDTH(64'd8), .value(8'hAA)) Constant8_80 (.out(wire_77)); + + wire [0:0] wire_0; + wire [0:0] wire_1; + wire [7:0] wire_2; + assign wire_2 = B; + wire [7:0] wire_3; + wire [0:0] wire_4; + wire [0:0] wire_5; + wire [7:0] wire_6; + assign wire_6 = A; + wire [0:0] wire_7; + wire [7:0] wire_8; + wire [7:0] wire_8_0; + wire [7:0] wire_8_1; + wire [7:0] wire_8_2; + wire [7:0] wire_8_3; + wire [7:0] wire_8_4; + wire [7:0] wire_8_5; + wire [7:0] wire_8_6; + assign wire_8 = wire_8_0|wire_8_1|wire_8_2|wire_8_3|wire_8_4|wire_8_5|wire_8_6; + wire [7:0] wire_9; + wire [7:0] wire_10; + wire [7:0] wire_11; + wire [7:0] wire_12; + wire [0:0] wire_13; + wire [0:0] wire_13_0; + wire [0:0] wire_13_1; + assign wire_13 = wire_13_0|wire_13_1; + assign CF = wire_13; + wire [7:0] wire_14; + wire [7:0] wire_15; + wire [7:0] wire_15_0; + wire [7:0] wire_15_1; + wire [7:0] wire_15_2; + wire [7:0] wire_15_3; + wire [7:0] wire_15_4; + assign wire_15 = wire_15_0|wire_15_1|wire_15_2|wire_15_3|wire_15_4; + wire [0:0] wire_16; + wire [7:0] wire_17; + wire [7:0] wire_18; + wire [7:0] wire_19; + wire [0:0] wire_20; + wire [0:0] wire_21; + wire [7:0] wire_22; + wire [7:0] wire_22_0; + wire [7:0] wire_22_1; + wire [7:0] wire_22_2; + wire [7:0] wire_22_3; + wire [7:0] wire_22_4; + assign wire_22 = wire_22_0|wire_22_1|wire_22_2|wire_22_3|wire_22_4; + wire [0:0] wire_23; + wire [0:0] wire_24; + wire [0:0] wire_25; + wire [0:0] wire_26; + wire [7:0] wire_27; + wire [0:0] wire_28; + wire [7:0] wire_29; + assign wire_29 = Instruction; + wire [0:0] wire_30; + wire [0:0] wire_31; + wire [7:0] wire_32; + wire [7:0] wire_32_0; + wire [7:0] wire_32_1; + wire [7:0] wire_32_2; + assign wire_32 = wire_32_0|wire_32_1|wire_32_2; + assign C = wire_32; + wire [7:0] wire_33; + wire [7:0] wire_34; + wire [0:0] wire_35; + assign D_OUT_EN = wire_35; + wire [7:0] wire_36; + wire [7:0] wire_37; + wire [7:0] wire_38; + wire [7:0] wire_39; + wire [7:0] wire_40; + wire [7:0] wire_41; + wire [0:0] wire_42; + wire [7:0] wire_43; + wire [7:0] wire_44; + wire [7:0] wire_44_0; + wire [7:0] wire_44_1; + assign wire_44 = wire_44_0|wire_44_1; + wire [7:0] wire_45; + wire [0:0] wire_46; + wire [7:0] wire_47; + wire [0:0] wire_48; + wire [7:0] wire_49; + wire [7:0] wire_50; + wire [7:0] wire_51; + wire [7:0] wire_52; + wire [7:0] wire_53; + wire [7:0] wire_54; + wire [0:0] wire_55; + wire [7:0] wire_56; + wire [7:0] wire_57; + wire [7:0] wire_58; + wire [7:0] wire_59; + wire [7:0] wire_60; + wire [0:0] wire_61; + wire [7:0] wire_62; + wire [7:0] wire_63; + wire [7:0] wire_64; + wire [7:0] wire_65; + wire [7:0] wire_66; + wire [7:0] wire_67; + wire [7:0] wire_68; + wire [0:0] wire_69; + wire [0:0] wire_70; + wire [7:0] wire_71; + wire [7:0] wire_72; + wire [7:0] wire_73; + wire [0:0] wire_74; + wire [0:0] wire_75; + wire [7:0] wire_76; + wire [7:0] wire_77; + wire [7:0] wire_78; + wire [7:0] wire_79; + wire [7:0] wire_80; + wire [7:0] wire_81; + wire [0:0] wire_82; + wire [7:0] wire_83; + wire [7:0] wire_84; + wire [7:0] wire_85; + wire [7:0] wire_86; + +endmodule diff --git a/src/verilog/ECP8_components/RegisterPlus.v b/src/verilog/ECP8_components/RegisterPlus.v new file mode 100644 index 0000000..fee3e45 --- /dev/null +++ b/src/verilog/ECP8_components/RegisterPlus.v @@ -0,0 +1,27 @@ +module RegisterPlus (clk, rst, Load, Save_value, Save, Always_output, Output); + parameter UUID = 0; + parameter NAME = ""; + input wire clk; + input wire rst; + + input wire [0:0] Load; + input wire [7:0] Save_value; + input wire [0:0] Save; + output wire [7:0] Always_output; + output wire [7:0] Output; + + TC_Register # (.UUID(64'd1 ^ UUID), .BIT_WIDTH(64'd8)) Register8_0 (.clk(clk), .rst(rst), .load(wire_2), .save(wire_4), .in(wire_0), .out(wire_3)); + TC_Constant # (.UUID(64'd2 ^ UUID), .BIT_WIDTH(64'd1), .value(1'd1)) On_1 (.out(wire_2)); + TC_Switch # (.UUID(64'd3587491547824661070 ^ UUID), .BIT_WIDTH(64'd8)) Output8z_2 (.en(wire_1), .in(wire_3), .out(Output)); + + wire [7:0] wire_0; + assign wire_0 = Save_value; + wire [0:0] wire_1; + assign wire_1 = Load; + wire [0:0] wire_2; + wire [7:0] wire_3; + assign Always_output = wire_3; + wire [0:0] wire_4; + assign wire_4 = Save; + +endmodule diff --git a/src/verilog/ECP8_components/subsys/COND.v b/src/verilog/ECP8_components/subsys/COND.v new file mode 100644 index 0000000..5c2e4b4 --- /dev/null +++ b/src/verilog/ECP8_components/subsys/COND.v @@ -0,0 +1,53 @@ +module COND (clk, rst, Condition, Input, Result); + parameter UUID = 0; + parameter NAME = ""; + input wire clk; + input wire rst; + + input wire [7:0] Condition; + input wire [7:0] Input; + output wire [0:0] Result; + + TC_Splitter8 # (.UUID(64'd1888394345583920379 ^ UUID)) Splitter8_0 (.in(wire_14), .out0(wire_5), .out1(wire_8), .out2(wire_1), .out3(), .out4(), .out5(), .out6(), .out7()); + TC_Splitter8 # (.UUID(64'd2530385753961839292 ^ UUID)) Splitter8_1 (.in(wire_17), .out0(wire_4), .out1(wire_13), .out2(wire_18), .out3(wire_3), .out4(wire_15), .out5(wire_9), .out6(wire_11), .out7(wire_0)); + TC_Nor # (.UUID(64'd1517918423970542383 ^ UUID), .BIT_WIDTH(64'd1)) Nor_2 (.in0(wire_4), .in1(wire_13), .out(wire_19)); + TC_Nor # (.UUID(64'd2736061366789794415 ^ UUID), .BIT_WIDTH(64'd1)) Nor_3 (.in0(wire_18), .in1(wire_3), .out(wire_23)); + TC_Nor # (.UUID(64'd3648822797009876962 ^ UUID), .BIT_WIDTH(64'd1)) Nor_4 (.in0(wire_15), .in1(wire_9), .out(wire_20)); + TC_Nor # (.UUID(64'd3623192028484125320 ^ UUID), .BIT_WIDTH(64'd1)) Nor_5 (.in0(wire_11), .in1(wire_0), .out(wire_21)); + TC_Nand # (.UUID(64'd1210610590039792679 ^ UUID), .BIT_WIDTH(64'd1)) Nand_6 (.in0(wire_19), .in1(wire_23), .out(wire_6)); + TC_Nand # (.UUID(64'd722301827588141756 ^ UUID), .BIT_WIDTH(64'd1)) Nand_7 (.in0(wire_20), .in1(wire_21), .out(wire_10)); + TC_Nor # (.UUID(64'd3626258032196188357 ^ UUID), .BIT_WIDTH(64'd1)) Nor_8 (.in0(wire_6), .in1(wire_10), .out(wire_16)); + TC_Switch # (.UUID(64'd2273941197800776416 ^ UUID), .BIT_WIDTH(64'd1)) Switch1_9 (.en(wire_5), .in(wire_16), .out(wire_2)); + TC_Switch # (.UUID(64'd1588245332332211989 ^ UUID), .BIT_WIDTH(64'd1)) Switch1_10 (.en(wire_8), .in(wire_0), .out(wire_22)); + TC_Or # (.UUID(64'd407901765067939990 ^ UUID), .BIT_WIDTH(64'd1)) Or_11 (.in0(wire_2), .in1(wire_22), .out(wire_7)); + TC_Xor # (.UUID(64'd4237747319249404280 ^ UUID), .BIT_WIDTH(64'd1)) Xor_12 (.in0(wire_1), .in1(wire_7), .out(wire_12)); + + wire [0:0] wire_0; + wire [0:0] wire_1; + wire [0:0] wire_2; + wire [0:0] wire_3; + wire [0:0] wire_4; + wire [0:0] wire_5; + wire [0:0] wire_6; + wire [0:0] wire_7; + wire [0:0] wire_8; + wire [0:0] wire_9; + wire [0:0] wire_10; + wire [0:0] wire_11; + wire [0:0] wire_12; + assign Result = wire_12; + wire [0:0] wire_13; + wire [7:0] wire_14; + assign wire_14 = Condition; + wire [0:0] wire_15; + wire [0:0] wire_16; + wire [7:0] wire_17; + assign wire_17 = Input; + wire [0:0] wire_18; + wire [0:0] wire_19; + wire [0:0] wire_20; + wire [0:0] wire_21; + wire [0:0] wire_22; + wire [0:0] wire_23; + +endmodule diff --git a/src/verilog/ECP8_components/subsys/DEC.v b/src/verilog/ECP8_components/subsys/DEC.v new file mode 100644 index 0000000..cb8c400 --- /dev/null +++ b/src/verilog/ECP8_components/subsys/DEC.v @@ -0,0 +1,29 @@ +module DEC (clk, rst, Instruction, IMM_EN, ALU_EN, COPY_EN, BRANCH_EN); + parameter UUID = 0; + parameter NAME = ""; + input wire clk; + input wire rst; + + input wire [7:0] Instruction; + output wire [0:0] IMM_EN; + output wire [0:0] ALU_EN; + output wire [0:0] COPY_EN; + output wire [0:0] BRANCH_EN; + + TC_Decoder2 # (.UUID(64'd954500439059266356 ^ UUID)) Decoder2_0 (.sel0(wire_6), .sel1(wire_1), .out0(wire_2), .out1(wire_3), .out2(wire_5), .out3(wire_0)); + TC_Splitter8 # (.UUID(64'd2677939290028462653 ^ UUID)) Splitter8_1 (.in(wire_4), .out0(), .out1(), .out2(), .out3(), .out4(), .out5(), .out6(wire_6), .out7(wire_1)); + + wire [0:0] wire_0; + assign BRANCH_EN = wire_0; + wire [0:0] wire_1; + wire [0:0] wire_2; + assign IMM_EN = wire_2; + wire [0:0] wire_3; + assign ALU_EN = wire_3; + wire [7:0] wire_4; + assign wire_4 = Instruction; + wire [0:0] wire_5; + assign COPY_EN = wire_5; + wire [0:0] wire_6; + +endmodule diff --git a/src/verilog/ECP8e.v b/src/verilog/ECP8e.v new file mode 100644 index 0000000..75404ff --- /dev/null +++ b/src/verilog/ECP8e.v @@ -0,0 +1,166 @@ +module ECP8e (clk, rst, arch_output_enable, arch_output_value, arch_input_enable, arch_input_value); + parameter UUID = 0; + parameter NAME = ""; + input wire clk; + input wire rst; + + output wire [0:0] arch_output_enable; + output wire [7:0] arch_output_value; + output wire [0:0] arch_input_enable; + input wire [7:0] arch_input_value; + + TC_Switch # (.UUID(64'd1715727152826423794 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_0 (.en(wire_50), .in(wire_48), .out(wire_41)); + TC_Halt # (.UUID(64'd2976448359382631736 ^ UUID)) Halt_1 (.clk(clk), .rst(rst), .en(wire_67)); + TC_Not # (.UUID(64'd2472047754744094114 ^ UUID), .BIT_WIDTH(64'd1)) Not_2 (.in(wire_61), .out(wire_67)); + TC_IOSwitch # (.UUID(64'd2352853726822514667 ^ UUID), .BIT_WIDTH(64'd8)) LevelOutputArch_3 (.in(wire_56), .en(wire_38), .out(arch_output_value)); + TC_Program8_1 # (.UUID(64'd2319742357034652024 ^ UUID), .DEFAULT_FILE_NAME("outport_test.bin"), .ARG_SIG("outport_test=%s")) Program8_1_4 (.clk(clk), .rst(rst), .address(wire_5), .out(wire_48)); + TC_Switch # (.UUID(64'd556654018140205888 ^ UUID), .BIT_WIDTH(64'd8)) LevelInputArch_5 (.en(wire_27), .in(arch_input_value), .out(wire_39)); + ALU # (.UUID(64'd3424272698184478142 ^ UUID)) ALU_6 (.clk(clk), .rst(rst), .Instruction(wire_41), .A(wire_35), .B(wire_75), .D_OUT_EN(wire_15), .D(wire_71), .CF(), .C(wire_66)); + TC_Ram # (.UUID(64'd1661974221341126710 ^ UUID), .WORD_WIDTH(64'd8), .WORD_COUNT(64'd64)) Ram_7 (.clk(clk), .rst(rst), .load(1'd0), .save(1'd0), .address(32'd0), .in0(64'd0), .in1(64'd0), .in2(64'd0), .in3(64'd0), .out0(), .out1(), .out2(), .out3()); + TC_Buffer # (.UUID(64'd3602924629092547678 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_8 (.in(wire_48), .out(wire_28)); + TC_Buffer # (.UUID(64'd1036402492479265627 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_9 (.in(wire_1), .out(wire_55)); + TC_Buffer # (.UUID(64'd3234323155509956945 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_10 (.in(wire_23), .out(wire_60)); + TC_Buffer # (.UUID(64'd2118082778336995084 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_11 (.in(wire_18), .out(wire_77)); + TC_Buffer # (.UUID(64'd3247628008814229228 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_12 (.in(wire_20), .out(wire_72)); + TC_Buffer # (.UUID(64'd3783645420539942969 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_13 (.in(wire_33), .out(wire_73)); + TC_Buffer # (.UUID(64'd101493406757515111 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_14 (.in(wire_31), .out(wire_43)); + TC_Buffer # (.UUID(64'd1648258134768700275 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_15 (.in(wire_2), .out(wire_56)); + TC_Buffer # (.UUID(64'd297196408869131089 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_16 (.in(wire_39), .out(wire_51)); + TC_Decoder3 # (.UUID(64'd319890292667874856 ^ UUID)) Decoder3_17 (.dis(wire_19), .sel0(wire_47), .sel1(wire_69), .sel2(wire_70), .out0(wire_32), .out1(wire_34), .out2(wire_46), .out3(wire_9), .out4(wire_7), .out5(wire_62), .out6(wire_26), .out7(wire_53)); + TC_Decoder3 # (.UUID(64'd4421418411989485663 ^ UUID)) Decoder3_18 (.dis(wire_19), .sel0(wire_52), .sel1(wire_58), .sel2(wire_4), .out0(wire_65), .out1(wire_44), .out2(wire_59), .out3(wire_54), .out4(wire_14), .out5(wire_21), .out6(wire_24), .out7(wire_42)); + TC_Splitter8 # (.UUID(64'd274394922392375603 ^ UUID)) Splitter8_19 (.in(wire_28), .out0(wire_52), .out1(wire_58), .out2(wire_4), .out3(wire_47), .out4(wire_69), .out5(wire_70), .out6(), .out7()); + TC_Maker16 # (.UUID(64'd4271331395148101399 ^ UUID)) Maker16_20 (.in0(wire_23), .in1(wire_18), .out(wire_64)); + TC_Xor # (.UUID(64'd4015117391550831776 ^ UUID), .BIT_WIDTH(64'd1)) Xor_21 (.in0(wire_45), .in1(wire_65), .out(wire_68)); + TC_Switch # (.UUID(64'd4445417212749692549 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_22 (.en(wire_26), .in(wire_51), .out(wire_6_1)); + TC_Switch # (.UUID(64'd556730729123347464 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_23 (.en(wire_24), .in(wire_17), .out(wire_2)); + TC_Buffer # (.UUID(64'd3347726601253752187 ^ UUID), .BIT_WIDTH(64'd1)) Buffer1_24 (.in(wire_10), .out(wire_50)); + TC_Switch # (.UUID(64'd1860343635038049181 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_25 (.en(wire_8), .in(wire_17), .out(wire_6_0)); + TC_Or # (.UUID(64'd4336129294321593228 ^ UUID), .BIT_WIDTH(64'd1)) Or_26 (.in0(wire_25), .in1(wire_3), .out(wire_45)); + TC_Xor # (.UUID(64'd1518074666294394017 ^ UUID), .BIT_WIDTH(64'd1)) Xor_27 (.in0(wire_54), .in1(wire_10), .out(wire_12)); + TC_Nand # (.UUID(64'd3859693831101792233 ^ UUID), .BIT_WIDTH(64'd1)) Nand_28 (.in0(wire_42), .in1(wire_53), .out(wire_22)); + TC_Switch # (.UUID(64'd1247979186234576792 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_29 (.en(wire_3), .in(wire_28), .out(wire_6_4)); + TC_Or3 # (.UUID(64'd4011049292989256787 ^ UUID), .BIT_WIDTH(64'd1)) Or3_30 (.in0(wire_3), .in1(wire_10), .in2(wire_25), .out(wire_19)); + TC_Switch # (.UUID(64'd2893193334261668714 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_31 (.en(wire_10), .in(wire_16), .out(wire_6_3)); + TC_And # (.UUID(64'd3005434726623612484 ^ UUID), .BIT_WIDTH(64'd1)) And_32 (.in0(wire_25), .in1(wire_76), .out(wire_49)); + TC_Switch # (.UUID(64'd929078426947889085 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_33 (.en(wire_25), .in(wire_28), .out(wire_63)); + TC_Counter # (.UUID(64'd3263272588803768522 ^ UUID), .BIT_WIDTH(64'd8), .count(8'd1)) Counter8_34 (.clk(clk), .rst(rst), .save(wire_49), .in(wire_1), .out(wire_5)); + TC_Buffer # (.UUID(64'd2235373354836046298 ^ UUID), .BIT_WIDTH(64'd1)) Buffer1_35 (.in(wire_22), .out(wire_61)); + TC_Buffer # (.UUID(64'd2032593801523540386 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_36 (.in(wire_5), .out()); + TC_Buffer # (.UUID(64'd2286316240340576623 ^ UUID), .BIT_WIDTH(64'd1)) Buffer1_37 (.in(wire_15), .out(wire_36)); + TC_Splitter16 # (.UUID(64'd2817158020377327923 ^ UUID)) Splitter16_38 (.in(wire_29), .out0(wire_16), .out1(wire_0)); + TC_Switch # (.UUID(64'd2251356442933710957 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_39 (.en(wire_36), .in(wire_0), .out(wire_6_2)); + TC_Buffer # (.UUID(64'd2774123988237700806 ^ UUID), .BIT_WIDTH(64'd1)) Buffer1_40 (.in(wire_24), .out(wire_38)); + TC_Buffer # (.UUID(64'd2259435457617166464 ^ UUID), .BIT_WIDTH(64'd1)) Buffer1_41 (.in(wire_26), .out(wire_27)); + TC_Nor # (.UUID(64'd28166036220749041 ^ UUID), .BIT_WIDTH(64'd1)) Nor_42 (.in0(wire_26), .in1(wire_24), .out(wire_37)); + TC_And # (.UUID(64'd2711603589399634934 ^ UUID), .BIT_WIDTH(64'd1)) And_43 (.in0(wire_40), .in1(wire_37), .out(wire_8)); + TC_Splitter16 # (.UUID(64'd4364533521657012903 ^ UUID)) Splitter16_44 (.in(wire_74), .out0(wire_11), .out1(wire_30)); + TC_Buffer # (.UUID(64'd1306800471778976915 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_45 (.in(wire_11), .out(wire_35)); + TC_Buffer # (.UUID(64'd4600618263124473635 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_46 (.in(wire_30), .out(wire_75)); + TC_Switch # (.UUID(64'd2102499097582599256 ^ UUID), .BIT_WIDTH(64'd16)) Switch16_47 (.en(wire_10), .in(wire_64), .out(wire_74)); + TC_Buffer # (.UUID(64'd1794452372346720268 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_48 (.in(wire_66), .out(wire_57)); + TC_Buffer # (.UUID(64'd3772267359649597453 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_49 (.in(wire_71), .out(wire_13)); + TC_Maker16 # (.UUID(64'd1181495850574424 ^ UUID)) Maker16_50 (.in0(wire_57), .in1(wire_13), .out(wire_29)); + RegisterPlus # (.UUID(64'd2661760033600874299 ^ UUID)) RegisterPlus_51 (.clk(clk), .rst(rst), .Load(wire_32), .Save_value(wire_6), .Save(wire_68), .Always_output(wire_1), .Output(wire_17_4)); + RegisterPlus # (.UUID(64'd2163217265803647012 ^ UUID)) RegisterPlus_52 (.clk(clk), .rst(rst), .Load(wire_34), .Save_value(wire_6), .Save(wire_44), .Always_output(wire_23), .Output(wire_17_5)); + RegisterPlus # (.UUID(64'd1347627285814452637 ^ UUID)) RegisterPlus_53 (.clk(clk), .rst(rst), .Load(wire_46), .Save_value(wire_6), .Save(wire_59), .Always_output(wire_18), .Output(wire_17_3)); + RegisterPlus # (.UUID(64'd3166915688793493761 ^ UUID)) RegisterPlus_54 (.clk(clk), .rst(rst), .Load(wire_9), .Save_value(wire_6), .Save(wire_12), .Always_output(wire_20), .Output(wire_17_2)); + RegisterPlus # (.UUID(64'd4519434156825869138 ^ UUID)) RegisterPlus_55 (.clk(clk), .rst(rst), .Load(wire_7), .Save_value(wire_6), .Save(wire_14), .Always_output(wire_33), .Output(wire_17_1)); + RegisterPlus # (.UUID(64'd3857793667730710479 ^ UUID)) RegisterPlus_56 (.clk(clk), .rst(rst), .Load(wire_62), .Save_value(wire_6), .Save(wire_21), .Always_output(wire_31), .Output(wire_17_0)); + DEC # (.UUID(64'd3963022757837899629 ^ UUID)) DEC_57 (.clk(clk), .rst(rst), .Instruction(wire_28), .IMM_EN(wire_3), .ALU_EN(wire_10), .COPY_EN(wire_40), .BRANCH_EN(wire_25)); + COND # (.UUID(64'd1986738645304097046 ^ UUID)) COND_58 (.clk(clk), .rst(rst), .Condition(wire_63), .Input(wire_20), .Result(wire_76)); + + wire [7:0] wire_0; + wire [7:0] wire_1; + wire [7:0] wire_2; + wire [0:0] wire_3; + wire [0:0] wire_4; + wire [7:0] wire_5; + wire [7:0] wire_6; + wire [7:0] wire_6_0; + wire [7:0] wire_6_1; + wire [7:0] wire_6_2; + wire [7:0] wire_6_3; + wire [7:0] wire_6_4; + assign wire_6 = wire_6_0|wire_6_1|wire_6_2|wire_6_3|wire_6_4; + wire [0:0] wire_7; + wire [0:0] wire_8; + wire [0:0] wire_9; + wire [0:0] wire_10; + wire [7:0] wire_11; + wire [0:0] wire_12; + wire [7:0] wire_13; + wire [0:0] wire_14; + wire [0:0] wire_15; + wire [7:0] wire_16; + wire [7:0] wire_17; + wire [7:0] wire_17_0; + wire [7:0] wire_17_1; + wire [7:0] wire_17_2; + wire [7:0] wire_17_3; + wire [7:0] wire_17_4; + wire [7:0] wire_17_5; + assign wire_17 = wire_17_0|wire_17_1|wire_17_2|wire_17_3|wire_17_4|wire_17_5; + wire [7:0] wire_18; + wire [0:0] wire_19; + wire [7:0] wire_20; + wire [0:0] wire_21; + wire [0:0] wire_22; + wire [7:0] wire_23; + wire [0:0] wire_24; + wire [0:0] wire_25; + wire [0:0] wire_26; + wire [0:0] wire_27; + assign arch_input_enable = wire_27; + wire [7:0] wire_28; + wire [15:0] wire_29; + wire [7:0] wire_30; + wire [7:0] wire_31; + wire [0:0] wire_32; + wire [7:0] wire_33; + wire [0:0] wire_34; + wire [7:0] wire_35; + wire [0:0] wire_36; + wire [0:0] wire_37; + wire [0:0] wire_38; + assign arch_output_enable = wire_38; + wire [7:0] wire_39; + wire [0:0] wire_40; + wire [7:0] wire_41; + wire [0:0] wire_42; + wire [7:0] wire_43; + wire [0:0] wire_44; + wire [0:0] wire_45; + wire [0:0] wire_46; + wire [0:0] wire_47; + wire [7:0] wire_48; + wire [0:0] wire_49; + wire [0:0] wire_50; + wire [7:0] wire_51; + wire [0:0] wire_52; + wire [0:0] wire_53; + wire [0:0] wire_54; + wire [7:0] wire_55; + wire [7:0] wire_56; + wire [7:0] wire_57; + wire [0:0] wire_58; + wire [0:0] wire_59; + wire [7:0] wire_60; + wire [0:0] wire_61; + wire [0:0] wire_62; + wire [7:0] wire_63; + wire [15:0] wire_64; + wire [0:0] wire_65; + wire [7:0] wire_66; + wire [0:0] wire_67; + wire [0:0] wire_68; + wire [0:0] wire_69; + wire [0:0] wire_70; + wire [7:0] wire_71; + wire [7:0] wire_72; + wire [7:0] wire_73; + wire [15:0] wire_74; + wire [7:0] wire_75; + wire [0:0] wire_76; + wire [7:0] wire_77; + +endmodule diff --git a/src/verilog/TC_Universe-iv.out b/src/verilog/TC_Universe-iv.out new file mode 100755 index 0000000..8abd5a7 --- /dev/null +++ b/src/verilog/TC_Universe-iv.out @@ -0,0 +1,6296 @@ +#! /usr/bin/vvp +:ivl_version "12.0 (stable)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 9; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; +S_0x55cf9db38d20 .scope module, "TC_Universe" "TC_Universe" 2 3; + .timescale -8 -9; +v0x55cf9dc31950_0 .var "clk", 0 0; +v0x55cf9dc31a10_0 .net "control_in", 0 0, L_0x55cf9dc513e0; 1 drivers +v0x55cf9dc31ad0_0 .net "control_out", 0 0, L_0x55cf9dc51560; 1 drivers +v0x55cf9dc31b70_0 .var "data_in", 7 0; +v0x55cf9dc31c60_0 .net "data_out", 7 0, L_0x55cf9dc323a0; 1 drivers +v0x55cf9dc31da0_0 .var/i "fd", 31 0; +v0x55cf9dc31e40_0 .var "file_name", 4096 0; +v0x55cf9dc31f20_0 .var/i "i", 31 0; +v0x55cf9dc32000_0 .var "index", 15 0; +v0x55cf9dc32170 .array "mem", 65535 0, 7 0; +v0x55cf9dc32230_0 .var "rst", 0 0; +E_0x55cf9d9d4910 .event posedge, v0x55cf9dc2bc50_0; +S_0x55cf9dbb0f60 .scope module, "dut" "ECP8e" 2 25, 3 1 0, S_0x55cf9db38d20; + .timescale -8 -9; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /OUTPUT 1 "arch_output_enable"; + .port_info 3 /OUTPUT 8 "arch_output_value"; + .port_info 4 /OUTPUT 1 "arch_input_enable"; + .port_info 5 /INPUT 8 "arch_input_value"; +P_0x55cf9db51540 .param/str "NAME" 0 3 3, "\000"; +P_0x55cf9db51580 .param/l "UUID" 0 3 2, +C4<00000000000000000000000000000000>; +L_0x55cf9dc50c10 .functor OR 8, v0x55cf9dc28000_0, v0x55cf9dc26dd0_0, C4<00000000>, C4<00000000>; +L_0x55cf9dc50ca0 .functor OR 8, L_0x55cf9dc50c10, v0x55cf9dc2a4e0_0, C4<00000000>, C4<00000000>; +L_0x55cf9dc50d30 .functor OR 8, L_0x55cf9dc50ca0, v0x55cf9dc292a0_0, C4<00000000>, C4<00000000>; +L_0x55cf9dc50da0 .functor OR 8, L_0x55cf9dc50d30, v0x55cf9dc28900_0, C4<00000000>, C4<00000000>; +L_0x55cf9dc50e10 .functor OR 8, v0x55cf9dc21d50_0, v0x55cf9dc1ee00_0, C4<00000000>, C4<00000000>; +L_0x55cf9dc50fa0 .functor OR 8, L_0x55cf9dc50e10, v0x55cf9dc1c1e0_0, C4<00000000>, C4<00000000>; +L_0x55cf9dc510e0 .functor OR 8, L_0x55cf9dc50fa0, v0x55cf9dc195b0_0, C4<00000000>, C4<00000000>; +L_0x55cf9dc511e0 .functor OR 8, L_0x55cf9dc510e0, v0x55cf9dc13c80_0, C4<00000000>, C4<00000000>; +L_0x55cf9dc512e0 .functor OR 8, L_0x55cf9dc511e0, v0x55cf9dc16990_0, C4<00000000>, C4<00000000>; +L_0x55cf9dc513e0 .functor BUFZ 1, L_0x55cf9dc4b690, C4<0>, C4<0>, C4<0>; +L_0x55cf9dc51560 .functor BUFZ 1, L_0x55cf9dc4b5e0, C4<0>, C4<0>, C4<0>; +v0x55cf9dc2b5d0_0 .net *"_ivl_14", 7 0, L_0x55cf9dc50c10; 1 drivers +v0x55cf9dc2b6b0_0 .net *"_ivl_16", 7 0, L_0x55cf9dc50ca0; 1 drivers +v0x55cf9dc2b790_0 .net *"_ivl_18", 7 0, L_0x55cf9dc50d30; 1 drivers +v0x55cf9dc2b880_0 .net *"_ivl_22", 7 0, L_0x55cf9dc50e10; 1 drivers +v0x55cf9dc2b960_0 .net *"_ivl_24", 7 0, L_0x55cf9dc50fa0; 1 drivers +v0x55cf9dc2ba90_0 .net *"_ivl_26", 7 0, L_0x55cf9dc510e0; 1 drivers +v0x55cf9dc2bb70_0 .net *"_ivl_28", 7 0, L_0x55cf9dc511e0; 1 drivers +v0x55cf9dc2bc50_0 .net "arch_input_enable", 0 0, L_0x55cf9dc513e0; alias, 1 drivers +v0x55cf9dc2bd30_0 .net "arch_input_value", 7 0, v0x55cf9dc31b70_0; 1 drivers +v0x55cf9dc2be80_0 .net "arch_output_enable", 0 0, L_0x55cf9dc51560; alias, 1 drivers +v0x55cf9dc2bf40_0 .net "arch_output_value", 7 0, L_0x55cf9dc323a0; alias, 1 drivers +v0x55cf9dc2c030_0 .net "clk", 0 0, v0x55cf9dc31950_0; 1 drivers +v0x55cf9dc2c0d0_0 .net "rst", 0 0, v0x55cf9dc32230_0; 1 drivers +v0x55cf9dc2c170_0 .net "wire_0", 7 0, L_0x55cf9dc4b360; 1 drivers +v0x55cf9dc2c210_0 .net "wire_1", 7 0, L_0x55cf9dc4c6a0; 1 drivers +v0x55cf9dc2c2d0_0 .net "wire_10", 0 0, L_0x55cf9dc4e430; 1 drivers +v0x55cf9dc2c390_0 .net "wire_11", 7 0, L_0x55cf9dc4ba40; 1 drivers +v0x55cf9dc2c4a0_0 .net "wire_12", 0 0, L_0x55cf9dc4a7b0; 1 drivers +v0x55cf9dc2c5b0_0 .net "wire_13", 7 0, L_0x55cf9dc4c190; 1 drivers +v0x55cf9dc2c6c0_0 .net "wire_14", 0 0, v0x55cf9dc0ab40_0; 1 drivers +v0x55cf9dc2c7d0_0 .net "wire_15", 0 0, L_0x55cf9dc49160; 1 drivers +v0x55cf9dc2c8e0_0 .net "wire_16", 7 0, L_0x55cf9dc4b400; 1 drivers +v0x55cf9dc2c9f0_0 .net "wire_17", 7 0, L_0x55cf9dc512e0; 1 drivers +v0x55cf9dc2cb00_0 .net "wire_17_0", 7 0, v0x55cf9dc21d50_0; 1 drivers +v0x55cf9dc2cc10_0 .net "wire_17_1", 7 0, v0x55cf9dc1ee00_0; 1 drivers +v0x55cf9dc2cd20_0 .net "wire_17_2", 7 0, v0x55cf9dc1c1e0_0; 1 drivers +v0x55cf9dc2ce30_0 .net "wire_17_3", 7 0, v0x55cf9dc195b0_0; 1 drivers +v0x55cf9dc2cf40_0 .net "wire_17_4", 7 0, v0x55cf9dc13c80_0; 1 drivers +v0x55cf9dc2d050_0 .net "wire_17_5", 7 0, v0x55cf9dc16990_0; 1 drivers +v0x55cf9dc2d160_0 .net "wire_18", 7 0, L_0x55cf9dc4ce40; 1 drivers +v0x55cf9dc2d220_0 .net "wire_19", 0 0, L_0x55cf9dc4ac00; 1 drivers +v0x55cf9dc2d2e0_0 .net "wire_2", 7 0, v0x55cf9dc27700_0; 1 drivers +v0x55cf9dc2d3f0_0 .net "wire_20", 7 0, L_0x55cf9dc4d140; 1 drivers +v0x55cf9dc2d6c0_0 .net "wire_21", 0 0, v0x55cf9dc0ac00_0; 1 drivers +v0x55cf9dc2d7d0_0 .net "wire_22", 0 0, L_0x55cf9dc4aa00; 1 drivers +v0x55cf9dc2d8e0_0 .net "wire_23", 7 0, L_0x55cf9dc4cb40; 1 drivers +v0x55cf9dc2d9a0_0 .net "wire_24", 0 0, v0x55cf9dc0acc0_0; 1 drivers +v0x55cf9dc2da60_0 .net "wire_25", 0 0, L_0x55cf9dc4e250; 1 drivers +v0x55cf9dc2db20_0 .net "wire_26", 0 0, v0x55cf9dc09c90_0; 1 drivers +v0x55cf9dc2dc70_0 .net "wire_27", 0 0, L_0x55cf9dc4b690; 1 drivers +v0x55cf9dc2dd30_0 .net "wire_28", 7 0, L_0x55cf9dc49410; 1 drivers +v0x55cf9dc2ddf0_0 .net "wire_29", 15 0, L_0x55cf9dc4c240; 1 drivers +v0x55cf9dc2deb0_0 .net "wire_3", 0 0, L_0x55cf9dc4e350; 1 drivers +v0x55cf9dc2e000_0 .net "wire_30", 7 0, L_0x55cf9dc4b9a0; 1 drivers +v0x55cf9dc2e0c0_0 .net "wire_31", 7 0, L_0x55cf9dc4d8b0; 1 drivers +v0x55cf9dc2e1d0_0 .net "wire_32", 0 0, v0x55cf9dc097b0_0; 1 drivers +v0x55cf9dc2e2e0_0 .net "wire_33", 7 0, L_0x55cf9dc4d4b0; 1 drivers +v0x55cf9dc2e3f0_0 .net "wire_34", 0 0, v0x55cf9dc09870_0; 1 drivers +v0x55cf9dc2e500_0 .net "wire_35", 7 0, L_0x55cf9dc4bb90; 1 drivers +v0x55cf9dc2e610_0 .net "wire_36", 0 0, L_0x55cf9dc4b220; 1 drivers +v0x55cf9dc2e720_0 .net "wire_37", 0 0, L_0x55cf9dc4b7d0; 1 drivers +v0x55cf9dc2e830_0 .net "wire_38", 0 0, L_0x55cf9dc4b5e0; 1 drivers +v0x55cf9dc2e940_0 .net "wire_39", 7 0, v0x55cf9dc0c230_0; 1 drivers +v0x55cf9dc2ea50_0 .net "wire_4", 0 0, L_0x55cf9dc49fc0; 1 drivers +v0x55cf9dc2eb60_0 .net "wire_40", 0 0, L_0x55cf9dc4e6b0; 1 drivers +v0x55cf9dc2ec70_0 .net "wire_41", 7 0, v0x55cf9dc264e0_0; 1 drivers +v0x55cf9dc2ed80_0 .net "wire_42", 0 0, v0x55cf9dc0ad60_0; 1 drivers +v0x55cf9dc2ee90_0 .net "wire_43", 7 0, L_0x55cf9dc49990; 1 drivers +v0x55cf9dc2ef50_0 .net "wire_44", 0 0, v0x55cf9dc0a8a0_0; 1 drivers +v0x55cf9dc2f040_0 .net "wire_45", 0 0, L_0x55cf9dc4a670; 1 drivers +v0x55cf9dc2f150_0 .net "wire_46", 0 0, v0x55cf9dc09940_0; 1 drivers +v0x55cf9dc2f260_0 .net "wire_47", 0 0, L_0x55cf9dc49f20; 1 drivers +v0x55cf9dc2f370_0 .net "wire_48", 7 0, v0x55cf9dc11140_0; 1 drivers +v0x55cf9dc2f430_0 .net "wire_49", 0 0, L_0x55cf9dc4ad70; 1 drivers +v0x55cf9dc2f540_0 .net "wire_5", 7 0, v0x55cf9dc06760_0; 1 drivers +v0x55cf9dc2f600_0 .net "wire_50", 0 0, L_0x55cf9dc4a530; 1 drivers +v0x55cf9dc2f710_0 .net "wire_51", 7 0, L_0x55cf9dc49b40; 1 drivers +v0x55cf9dc2f820_0 .net "wire_52", 0 0, L_0x55cf9dc4a140; 1 drivers +v0x55cf9dc2f930_0 .net "wire_53", 0 0, v0x55cf9dc09d30_0; 1 drivers +v0x55cf9dc2fa40_0 .net "wire_54", 0 0, v0x55cf9dc0aa30_0; 1 drivers +v0x55cf9dc2fb50_0 .net "wire_55", 7 0, L_0x55cf9dc49480; 1 drivers +v0x55cf9dc2fc10_0 .net "wire_56", 7 0, L_0x55cf9dc49a90; 1 drivers +v0x55cf9dc2fd00_0 .net "wire_57", 7 0, L_0x55cf9dc4c050; 1 drivers +v0x55cf9dc2fe10_0 .net "wire_58", 0 0, L_0x55cf9dc4a0a0; 1 drivers +v0x55cf9dc2ff20_0 .net "wire_59", 0 0, v0x55cf9dc0a970_0; 1 drivers +v0x55cf9dc30030_0 .net "wire_6", 7 0, L_0x55cf9dc50da0; 1 drivers +v0x55cf9dc300f0_0 .net "wire_60", 7 0, L_0x55cf9dc49580; 1 drivers +v0x55cf9dc301b0_0 .net "wire_61", 0 0, L_0x55cf9dc4afc0; 1 drivers +v0x55cf9dc302a0_0 .net "wire_62", 0 0, v0x55cf9dc09bd0_0; 1 drivers +v0x55cf9dc303b0_0 .net "wire_63", 7 0, v0x55cf9dc29c80_0; 1 drivers +v0x55cf9dc304c0_0 .net "wire_64", 15 0, L_0x55cf9dc4a2a0; 1 drivers +v0x55cf9dc305d0_0 .net "wire_65", 0 0, v0x55cf9dc0a800_0; 1 drivers +v0x55cf9dc306e0_0 .net "wire_66", 7 0, L_0x55cf9dc48fe0; 1 drivers +v0x55cf9dc307f0_0 .net "wire_67", 0 0, L_0x55cf9dc322f0; 1 drivers +v0x55cf9dc30900_0 .net "wire_68", 0 0, L_0x55cf9dc4a360; 1 drivers +v0x55cf9dc30a10_0 .net "wire_69", 0 0, L_0x55cf9dc49dc0; 1 drivers +v0x55cf9dc30b20_0 .net "wire_6_0", 7 0, v0x55cf9dc28000_0; 1 drivers +v0x55cf9dc30be0_0 .net "wire_6_1", 7 0, v0x55cf9dc26dd0_0; 1 drivers +v0x55cf9dc30c80_0 .net "wire_6_2", 7 0, v0x55cf9dc2a4e0_0; 1 drivers +v0x55cf9dc30d20_0 .net "wire_6_3", 7 0, v0x55cf9dc292a0_0; 1 drivers +v0x55cf9dc30dc0_0 .net "wire_6_4", 7 0, v0x55cf9dc28900_0; 1 drivers +v0x55cf9dc30e60_0 .net "wire_7", 0 0, v0x55cf9dc09b10_0; 1 drivers +v0x55cf9dc30f50_0 .net "wire_70", 0 0, L_0x55cf9dc49d20; 1 drivers +v0x55cf9dc31060_0 .net "wire_71", 7 0, v0x55cf9db59750_0; 1 drivers +v0x55cf9dc31120_0 .net "wire_72", 7 0, L_0x55cf9dc497a0; 1 drivers +v0x55cf9dc311e0_0 .net "wire_73", 7 0, L_0x55cf9dc498e0; 1 drivers +v0x55cf9dc31280_0 .net "wire_74", 15 0, v0x55cf9dc25be0_0; 1 drivers +v0x55cf9dc31370_0 .net "wire_75", 7 0, L_0x55cf9dc4bd60; 1 drivers +v0x55cf9dc31480_0 .net "wire_76", 0 0, L_0x55cf9dc50920; 1 drivers +v0x55cf9dc31590_0 .net "wire_77", 7 0, L_0x55cf9dc49680; 1 drivers +v0x55cf9dc31650_0 .net "wire_8", 0 0, L_0x55cf9dc4b860; 1 drivers +v0x55cf9dc31740_0 .net "wire_9", 0 0, v0x55cf9dc09a00_0; 1 drivers +S_0x55cf9dbb4260 .scope module, "ALU_6" "ALU" 3 18, 4 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 8 "Instruction"; + .port_info 3 /INPUT 8 "A"; + .port_info 4 /INPUT 8 "B"; + .port_info 5 /OUTPUT 1 "D_OUT_EN"; + .port_info 6 /OUTPUT 8 "D"; + .port_info 7 /OUTPUT 1 "CF"; + .port_info 8 /OUTPUT 8 "C"; +P_0x55cf9db4c150 .param/str "NAME" 0 4 3, "\000"; +P_0x55cf9db4c190 .param/l "UUID" 0 4 2, C4<0010111110000101011101011110000001011101010110101010110110111110>; +L_0x55cf9dc47ef0 .functor BUFZ 8, L_0x55cf9dc4bd60, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x55cf9dc47f80 .functor BUFZ 8, L_0x55cf9dc4bb90, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x55cf9dc48010 .functor OR 8, v0x55cf9d94b6c0_0, v0x55cf9da209f0_0, C4<00000000>, C4<00000000>; +L_0x55cf9dc480d0 .functor OR 8, L_0x55cf9dc48010, v0x55cf9d9b4310_0, C4<00000000>, C4<00000000>; +L_0x55cf9dc481a0 .functor OR 8, L_0x55cf9dc480d0, v0x55cf9da25470_0, C4<00000000>, C4<00000000>; +L_0x55cf9dc48210 .functor OR 8, L_0x55cf9dc481a0, v0x55cf9dbd7680_0, C4<00000000>, C4<00000000>; +L_0x55cf9dc482c0 .functor OR 8, L_0x55cf9dc48210, v0x55cf9dbd5c20_0, C4<00000000>, C4<00000000>; +L_0x55cf9dc48330 .functor OR 8, L_0x55cf9dc482c0, v0x55cf9dbd88b0_0, C4<00000000>, C4<00000000>; +L_0x55cf9dc48490 .functor OR 1, v0x55cf9da26ff0_0, v0x55cf9da21350_0, C4<0>, C4<0>; +L_0x55cf9dc48500 .functor BUFZ 1, L_0x55cf9dc48490, C4<0>, C4<0>, C4<0>; +L_0x55cf9dc48620 .functor OR 8, v0x55cf9dbe62f0_0, v0x55cf9dbe6c00_0, C4<00000000>, C4<00000000>; +L_0x55cf9dc48690 .functor OR 8, L_0x55cf9dc48620, v0x55cf9dbe50d0_0, C4<00000000>, C4<00000000>; +L_0x55cf9dc48770 .functor OR 8, L_0x55cf9dc48690, v0x55cf9dbdbe80_0, C4<00000000>, C4<00000000>; +L_0x55cf9dc48830 .functor OR 8, L_0x55cf9dc48770, v0x55cf9dbe59e0_0, C4<00000000>, C4<00000000>; +L_0x55cf9dc48700 .functor OR 8, v0x55cf9dbde1f0_0, v0x55cf9dbdf410_0, C4<00000000>, C4<00000000>; +L_0x55cf9dc489e0 .functor OR 8, L_0x55cf9dc48700, v0x55cf9da75b60_0, C4<00000000>, C4<00000000>; +L_0x55cf9dc48b30 .functor OR 8, L_0x55cf9dc489e0, v0x55cf9dbda2e0_0, C4<00000000>, C4<00000000>; +L_0x55cf9dc48bf0 .functor OR 8, L_0x55cf9dc48b30, v0x55cf9dbdb460_0, C4<00000000>, C4<00000000>; +L_0x55cf9dc48da0 .functor BUFZ 8, v0x55cf9dc264e0_0, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x55cf9dc48e30 .functor OR 8, v0x55cf9dbe88b0_0, v0x55cf9dbe7f80_0, C4<00000000>, C4<00000000>; +L_0x55cf9dc48f70 .functor OR 8, L_0x55cf9dc48e30, v0x55cf9dbe7640_0, C4<00000000>, C4<00000000>; +L_0x55cf9dc48fe0 .functor BUFZ 8, L_0x55cf9dc48f70, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x55cf9dc49160 .functor BUFZ 1, L_0x55cf9dc479b0, C4<0>, C4<0>, C4<0>; +L_0x55cf9dc49280 .functor OR 8, v0x55cf9dbdeb00_0, v0x55cf9dbdfd20_0, C4<00000000>, C4<00000000>; +v0x55cf9dbeb310_0 .net "A", 7 0, L_0x55cf9dc4bb90; alias, 1 drivers +v0x55cf9dbeb3f0_0 .net "B", 7 0, L_0x55cf9dc4bd60; alias, 1 drivers +v0x55cf9dbeb4d0_0 .net "C", 7 0, L_0x55cf9dc48fe0; alias, 1 drivers +v0x55cf9dbeb5c0_0 .net "CF", 0 0, L_0x55cf9dc48500; 1 drivers +v0x55cf9dbeb6a0_0 .net "D", 7 0, v0x55cf9db59750_0; alias, 1 drivers +v0x55cf9dbeb7b0_0 .net "D_OUT_EN", 0 0, L_0x55cf9dc49160; alias, 1 drivers +v0x55cf9dbeb870_0 .net "Instruction", 7 0, v0x55cf9dc264e0_0; alias, 1 drivers +v0x55cf9dbeb950_0 .net *"_ivl_12", 7 0, L_0x55cf9dc48010; 1 drivers +v0x55cf9dbeba30_0 .net *"_ivl_14", 7 0, L_0x55cf9dc480d0; 1 drivers +v0x55cf9dbebb10_0 .net *"_ivl_16", 7 0, L_0x55cf9dc481a0; 1 drivers +v0x55cf9dbebbf0_0 .net *"_ivl_18", 7 0, L_0x55cf9dc48210; 1 drivers +v0x55cf9dbebcd0_0 .net *"_ivl_20", 7 0, L_0x55cf9dc482c0; 1 drivers +v0x55cf9dbebdb0_0 .net *"_ivl_28", 7 0, L_0x55cf9dc48620; 1 drivers +v0x55cf9dbebe90_0 .net *"_ivl_30", 7 0, L_0x55cf9dc48690; 1 drivers +v0x55cf9dbebf70_0 .net *"_ivl_32", 7 0, L_0x55cf9dc48770; 1 drivers +v0x55cf9dbec050_0 .net *"_ivl_36", 7 0, L_0x55cf9dc48700; 1 drivers +v0x55cf9dbec130_0 .net *"_ivl_38", 7 0, L_0x55cf9dc489e0; 1 drivers +v0x55cf9dbec210_0 .net *"_ivl_40", 7 0, L_0x55cf9dc48b30; 1 drivers +v0x55cf9dbec2f0_0 .net *"_ivl_46", 7 0, L_0x55cf9dc48e30; 1 drivers +v0x55cf9dbec3d0_0 .net "clk", 0 0, v0x55cf9dc31950_0; alias, 1 drivers +v0x55cf9dbec490_0 .net "rst", 0 0, v0x55cf9dc32230_0; alias, 1 drivers +v0x55cf9dbec550_0 .net "wire_0", 0 0, v0x55cf9db83080_0; 1 drivers +v0x55cf9dbec610_0 .net "wire_1", 0 0, v0x55cf9db89ee0_0; 1 drivers +v0x55cf9dbec6d0_0 .net "wire_10", 7 0, L_0x55cf9dc47b80; 1 drivers +v0x55cf9dbec790_0 .net "wire_11", 7 0, v0x55cf9dbdab70_0; 1 drivers +v0x55cf9dbec850_0 .net "wire_12", 7 0, v0x55cf9dbd4060_0; 1 drivers +v0x55cf9dbec960_0 .net "wire_13", 0 0, L_0x55cf9dc48490; 1 drivers +v0x55cf9dbeca40_0 .net "wire_13_0", 0 0, v0x55cf9da26ff0_0; 1 drivers +v0x55cf9dbecb00_0 .net "wire_13_1", 0 0, v0x55cf9da21350_0; 1 drivers +v0x55cf9dbecba0_0 .net "wire_14", 7 0, L_0x55cf9dc34590; 1 drivers +v0x55cf9dbecc90_0 .net "wire_15", 7 0, L_0x55cf9dc48830; 1 drivers +v0x55cf9dbecd50_0 .net "wire_15_0", 7 0, v0x55cf9dbe62f0_0; 1 drivers +v0x55cf9dbecdf0_0 .net "wire_15_1", 7 0, v0x55cf9dbe6c00_0; 1 drivers +v0x55cf9dbed0d0_0 .net "wire_15_2", 7 0, v0x55cf9dbe50d0_0; 1 drivers +v0x55cf9dbed1a0_0 .net "wire_15_3", 7 0, v0x55cf9dbdbe80_0; 1 drivers +v0x55cf9dbed270_0 .net "wire_15_4", 7 0, v0x55cf9dbe59e0_0; 1 drivers +v0x55cf9dbed340_0 .net "wire_16", 0 0, v0x55cf9db87240_0; 1 drivers +v0x55cf9dbed3e0_0 .net "wire_17", 7 0, v0x55cf9dbe2ea0_0; 1 drivers +v0x55cf9dbed4f0_0 .net "wire_18", 7 0, L_0x55cf9dc455a0; 1 drivers +v0x55cf9dbed600_0 .net "wire_19", 7 0, v0x55cf9dbd99f0_0; 1 drivers +v0x55cf9dbed710_0 .net "wire_2", 7 0, L_0x55cf9dc47ef0; 1 drivers +v0x55cf9dbed7d0_0 .net "wire_20", 0 0, v0x55cf9db7af30_0; 1 drivers +v0x55cf9dbed8e0_0 .net "wire_21", 0 0, L_0x55cf9dc32b50; 1 drivers +v0x55cf9dbed9f0_0 .net "wire_22", 7 0, L_0x55cf9dc48bf0; 1 drivers +v0x55cf9dbedab0_0 .net "wire_22_0", 7 0, v0x55cf9dbde1f0_0; 1 drivers +v0x55cf9dbedb50_0 .net "wire_22_1", 7 0, v0x55cf9dbdf410_0; 1 drivers +v0x55cf9dbedbf0_0 .net "wire_22_2", 7 0, v0x55cf9da75b60_0; 1 drivers +v0x55cf9dbedc90_0 .net "wire_22_3", 7 0, v0x55cf9dbda2e0_0; 1 drivers +v0x55cf9dbedd30_0 .net "wire_22_4", 7 0, v0x55cf9dbdb460_0; 1 drivers +v0x55cf9dbede00_0 .net "wire_23", 0 0, L_0x55cf9dc333e0; 1 drivers +v0x55cf9dbedef0_0 .net "wire_24", 0 0, v0x55cf9db86500_0; 1 drivers +v0x55cf9dbedfb0_0 .net "wire_25", 0 0, v0x55cf9db7c8f0_0; 1 drivers +v0x55cf9dbee0c0_0 .net "wire_26", 0 0, v0x55cf9db82370_0; 1 drivers +v0x55cf9dbee180_0 .net "wire_27", 7 0, L_0x55cf9dc34920; 1 drivers +v0x55cf9dbee290_0 .net "wire_28", 0 0, L_0x55cf9dc47900; 1 drivers +v0x55cf9dbee3a0_0 .net "wire_29", 7 0, L_0x55cf9dc48da0; 1 drivers +v0x55cf9dbee460_0 .net "wire_3", 7 0, L_0x55cf9dc34f10; 1 drivers +v0x55cf9dbee550_0 .net "wire_30", 0 0, v0x55cf9db7bc10_0; 1 drivers +v0x55cf9dbee610_0 .net "wire_31", 0 0, L_0x55cf9dc32600; 1 drivers +v0x55cf9dbee720_0 .net "wire_32", 7 0, L_0x55cf9dc48f70; 1 drivers +v0x55cf9dbee800_0 .net "wire_32_0", 7 0, v0x55cf9dbe88b0_0; 1 drivers +v0x55cf9dbee8c0_0 .net "wire_32_1", 7 0, v0x55cf9dbe7f80_0; 1 drivers +v0x55cf9dbee960_0 .net "wire_32_2", 7 0, v0x55cf9dbe7640_0; 1 drivers +v0x55cf9dbeea00_0 .net "wire_33", 7 0, L_0x55cf9dc32bf0; 1 drivers +v0x55cf9dbeeaf0_0 .net "wire_34", 7 0, v0x55cf9da38680_0; 1 drivers +v0x55cf9dbef010_0 .net "wire_35", 0 0, L_0x55cf9dc479b0; 1 drivers +v0x55cf9dbef120_0 .net "wire_36", 7 0, L_0x55cf9dc34270; 1 drivers +v0x55cf9dbef230_0 .net "wire_37", 7 0, v0x55cf9da2bb00_0; 1 drivers +v0x55cf9dbef340_0 .net "wire_38", 7 0, L_0x55cf9dc457e0; 1 drivers +v0x55cf9dbef450_0 .net "wire_39", 7 0, v0x55cf9d9a4010_0; 1 drivers +v0x55cf9dbef560_0 .net "wire_4", 0 0, v0x55cf9db87f80_0; 1 drivers +v0x55cf9dbef620_0 .net "wire_40", 7 0, L_0x55cf9dc34a90; 1 drivers +v0x55cf9dbef730_0 .net "wire_41", 7 0, v0x55cf9d975290_0; 1 drivers +v0x55cf9dbef840_0 .net "wire_42", 0 0, L_0x55cf9dc326a0; 1 drivers +v0x55cf9dbef950_0 .net "wire_43", 7 0, L_0x55cf9dc34dd0; 1 drivers +v0x55cf9dbefa60_0 .net "wire_44", 7 0, L_0x55cf9dc49280; 1 drivers +v0x55cf9dbefb20_0 .net "wire_44_0", 7 0, v0x55cf9dbdeb00_0; 1 drivers +v0x55cf9dbefbc0_0 .net "wire_44_1", 7 0, v0x55cf9dbdfd20_0; 1 drivers +v0x55cf9dbefc60_0 .net "wire_45", 7 0, L_0x55cf9dc332d0; 1 drivers +v0x55cf9dbefd50_0 .net "wire_46", 0 0, v0x55cf9db7a2f0_0; 1 drivers +v0x55cf9dbefe10_0 .net "wire_47", 7 0, v0x55cf9dbe0f20_0; 1 drivers +v0x55cf9dbeff00_0 .net "wire_48", 0 0, v0x55cf9db81660_0; 1 drivers +v0x55cf9dbeffc0_0 .net "wire_49", 7 0, v0x55cf9dbd6d60_0; 1 drivers +v0x55cf9dbf00b0_0 .net "wire_5", 0 0, v0x55cf9db52ea0_0; 1 drivers +v0x55cf9dbf0170_0 .net "wire_50", 7 0, v0x55cf9dbe47e0_0; 1 drivers +v0x55cf9dbf0280_0 .net "wire_51", 7 0, v0x55cf9dbdd900_0; 1 drivers +v0x55cf9dbf0390_0 .net "wire_52", 7 0, L_0x55cf9dc34600; 1 drivers +v0x55cf9dbf04a0_0 .net "wire_53", 7 0, v0x55cf9dbd91d0_0; 1 drivers +v0x55cf9dbf05b0_0 .net "wire_54", 7 0, v0x55cf9dbe18a0_0; 1 drivers +v0x55cf9dbf06c0_0 .net "wire_55", 0 0, L_0x55cf9dc32870; 1 drivers +v0x55cf9dbf07d0_0 .net "wire_56", 7 0, v0x55cf9dbdcf80_0; 1 drivers +v0x55cf9dbf08e0_0 .net "wire_57", 7 0, v0x55cf9dbe3710_0; 1 drivers +v0x55cf9dbf09f0_0 .net "wire_58", 7 0, v0x55cf9dbd7fa0_0; 1 drivers +v0x55cf9dbf0b00_0 .net "wire_59", 7 0, L_0x55cf9dc34a20; 1 drivers +v0x55cf9dbf0c10_0 .net "wire_6", 7 0, L_0x55cf9dc47f80; 1 drivers +v0x55cf9dbf0cd0_0 .net "wire_60", 7 0, v0x55cf9da1fe30_0; 1 drivers +v0x55cf9dbf0de0_0 .net "wire_61", 0 0, v0x55cf9db79540_0; 1 drivers +v0x55cf9dbf0ea0_0 .net "wire_62", 7 0, L_0x55cf9dc33480; 1 drivers +v0x55cf9dbf0f90_0 .net "wire_63", 7 0, L_0x55cf9dc34b00; 1 drivers +v0x55cf9dbf10a0_0 .net "wire_64", 7 0, v0x55cf9dbd4a10_0; 1 drivers +v0x55cf9dbf11b0_0 .net "wire_65", 7 0, L_0x55cf9dc34c10; 1 drivers +v0x55cf9dbf12c0_0 .net "wire_66", 7 0, v0x55cf9d9a6e90_0; 1 drivers +v0x55cf9dbf13d0_0 .net "wire_67", 7 0, L_0x55cf9dc34e70; 1 drivers +v0x55cf9dbf14e0_0 .net "wire_68", 7 0, v0x55cf9dbea230_0; 1 drivers +v0x55cf9dbf15f0_0 .net "wire_69", 0 0, L_0x55cf9dc327d0; 1 drivers +v0x55cf9dbf1700_0 .net "wire_7", 0 0, L_0x55cf9dc329f0; 1 drivers +v0x55cf9dbf1810_0 .net "wire_70", 0 0, v0x55cf9db78830_0; 1 drivers +v0x55cf9dbf18d0_0 .net "wire_71", 7 0, v0x55cf9d9b4d60_0; 1 drivers +v0x55cf9dbf19c0_0 .net "wire_72", 7 0, v0x55cf9dbd37c0_0; 1 drivers +v0x55cf9dbf1ad0_0 .net "wire_73", 7 0, v0x55cf9da2e240_0; 1 drivers +v0x55cf9dbf1be0_0 .net "wire_74", 0 0, v0x55cf9db7a250_0; 1 drivers +v0x55cf9dbf1ca0_0 .net "wire_75", 0 0, v0x55cf9db7afd0_0; 1 drivers +v0x55cf9dbf1d40_0 .net "wire_76", 7 0, v0x55cf9dbe2630_0; 1 drivers +L_0x7fcf8ba88408 .functor BUFT 1, C4<10101010>, C4<0>, C4<0>, C4<0>; +v0x55cf9dbf1e30_0 .net "wire_77", 7 0, L_0x7fcf8ba88408; 1 drivers +v0x55cf9dbf1f40_0 .net "wire_78", 7 0, L_0x55cf9dc47cd0; 1 drivers +v0x55cf9dbf2050_0 .net "wire_79", 7 0, v0x55cf9dbdc710_0; 1 drivers +v0x55cf9dbf2160_0 .net "wire_8", 7 0, L_0x55cf9dc48330; 1 drivers +v0x55cf9dbf2220_0 .net "wire_80", 7 0, L_0x55cf9dc34b70; 1 drivers +v0x55cf9dbf2310_0 .net "wire_81", 7 0, v0x55cf9dbd6530_0; 1 drivers +v0x55cf9dbf2420_0 .net "wire_82", 0 0, L_0x55cf9dc32950; 1 drivers +v0x55cf9dbf2530_0 .net "wire_83", 7 0, L_0x55cf9dc45880; 1 drivers +v0x55cf9dbf2640_0 .net "wire_84", 7 0, v0x55cf9dbd5320_0; 1 drivers +v0x55cf9dbf2750_0 .net "wire_85", 7 0, v0x55cf9dbe3f70_0; 1 drivers +v0x55cf9dbf2860_0 .net "wire_86", 7 0, v0x55cf9dbe99c0_0; 1 drivers +v0x55cf9dbf2970_0 .net "wire_8_0", 7 0, v0x55cf9d94b6c0_0; 1 drivers +v0x55cf9dbf2a30_0 .net "wire_8_1", 7 0, v0x55cf9da209f0_0; 1 drivers +v0x55cf9dbf2ad0_0 .net "wire_8_2", 7 0, v0x55cf9d9b4310_0; 1 drivers +v0x55cf9dbf2b70_0 .net "wire_8_3", 7 0, v0x55cf9da25470_0; 1 drivers +v0x55cf9dbf2c10_0 .net "wire_8_4", 7 0, v0x55cf9dbd7680_0; 1 drivers +v0x55cf9dbf34c0_0 .net "wire_8_5", 7 0, v0x55cf9dbd5c20_0; 1 drivers +v0x55cf9dbf3560_0 .net "wire_8_6", 7 0, v0x55cf9dbd88b0_0; 1 drivers +v0x55cf9dbf3600_0 .net "wire_9", 7 0, v0x55cf9dbe06c0_0; 1 drivers +S_0x55cf9dbb78e0 .scope module, "Add8_2" "TC_Add" 4 17, 5 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in0"; + .port_info 1 /INPUT 8 "in1"; + .port_info 2 /INPUT 1 "ci"; + .port_info 3 /OUTPUT 8 "out"; + .port_info 4 /OUTPUT 1 "co"; +P_0x55cf9db7f8e0 .param/l "BIT_WIDTH" 0 5 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9db7f920 .param/str "NAME" 0 5 3, "\000"; +P_0x55cf9db7f960 .param/l "UUID" 0 5 2, C4<0011100101111000110110110011011010111101001010101001001100110000>; +L_0x7fcf8ba880a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55cf9db6db90_0 .net *"_ivl_10", 0 0, L_0x7fcf8ba880a8; 1 drivers +v0x55cf9db6cde0_0 .net *"_ivl_11", 8 0, L_0x55cf9dc32e70; 1 drivers +L_0x7fcf8ba887f8 .functor BUFT 1, C4<000000000>, C4<0>, C4<0>, C4<0>; +v0x55cf9db6ceb0_0 .net *"_ivl_13", 8 0, L_0x7fcf8ba887f8; 1 drivers +v0x55cf9db51600_0 .net *"_ivl_17", 8 0, L_0x55cf9dc33020; 1 drivers +v0x55cf9db4c210_0 .net *"_ivl_3", 8 0, L_0x55cf9dc32c90; 1 drivers +L_0x7fcf8ba88060 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55cf9dbc1650_0 .net *"_ivl_6", 0 0, L_0x7fcf8ba88060; 1 drivers +v0x55cf9dbbe2f0_0 .net *"_ivl_7", 8 0, L_0x55cf9dc32d80; 1 drivers +L_0x7fcf8ba880f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55cf9dbbdfd0_0 .net "ci", 0 0, L_0x7fcf8ba880f0; 1 drivers +v0x55cf9dbbac70_0 .net "co", 0 0, L_0x55cf9dc32b50; alias, 1 drivers +v0x55cf9dbba950_0 .net "in0", 7 0, v0x55cf9dbe99c0_0; alias, 1 drivers +v0x55cf9dbb75f0_0 .net "in1", 7 0, L_0x55cf9dc332d0; alias, 1 drivers +v0x55cf9dbb72d0_0 .net "out", 7 0, L_0x55cf9dc32bf0; alias, 1 drivers +L_0x55cf9dc32b50 .part L_0x55cf9dc33020, 8, 1; +L_0x55cf9dc32bf0 .part L_0x55cf9dc33020, 0, 8; +L_0x55cf9dc32c90 .concat [ 8 1 0 0], v0x55cf9dbe99c0_0, L_0x7fcf8ba88060; +L_0x55cf9dc32d80 .concat [ 8 1 0 0], L_0x55cf9dc332d0, L_0x7fcf8ba880a8; +L_0x55cf9dc32e70 .arith/sum 9, L_0x55cf9dc32c90, L_0x55cf9dc32d80; +L_0x55cf9dc33020 .arith/sum 9, L_0x55cf9dc32e70, L_0x7fcf8ba887f8; +S_0x55cf9dbbaf60 .scope module, "Add8_7" "TC_Add" 4 22, 5 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in0"; + .port_info 1 /INPUT 8 "in1"; + .port_info 2 /INPUT 1 "ci"; + .port_info 3 /OUTPUT 8 "out"; + .port_info 4 /OUTPUT 1 "co"; +P_0x55cf9db76a20 .param/l "BIT_WIDTH" 0 5 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9db76a60 .param/str "NAME" 0 5 3, "\000"; +P_0x55cf9db76aa0 .param/l "UUID" 0 5 2, C4<0000111101010000010010110011011100111101101101010110000001110010>; +L_0x7fcf8ba881c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55cf9dbb3f70_0 .net *"_ivl_10", 0 0, L_0x7fcf8ba881c8; 1 drivers +v0x55cf9dbb4010_0 .net *"_ivl_11", 8 0, L_0x55cf9dc337d0; 1 drivers +L_0x7fcf8ba88840 .functor BUFT 1, C4<000000000>, C4<0>, C4<0>, C4<0>; +v0x55cf9dbb3c50_0 .net *"_ivl_13", 8 0, L_0x7fcf8ba88840; 1 drivers +v0x55cf9dbb08c0_0 .net *"_ivl_17", 8 0, L_0x55cf9dc33910; 1 drivers +v0x55cf9dbb05a0_0 .net *"_ivl_3", 8 0, L_0x55cf9dc33570; 1 drivers +L_0x7fcf8ba88180 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55cf9db3a250_0 .net *"_ivl_6", 0 0, L_0x7fcf8ba88180; 1 drivers +v0x55cf9db3de60_0 .net *"_ivl_7", 8 0, L_0x55cf9dc336a0; 1 drivers +L_0x7fcf8ba88210 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55cf9dbc4690_0 .net "ci", 0 0, L_0x7fcf8ba88210; 1 drivers +v0x55cf9dbcd280_0 .net "co", 0 0, L_0x55cf9dc333e0; alias, 1 drivers +v0x55cf9dbccf30_0 .net "in0", 7 0, v0x55cf9dbd5320_0; alias, 1 drivers +v0x55cf9dbcac10_0 .net "in1", 7 0, v0x55cf9dbd37c0_0; alias, 1 drivers +v0x55cf9dbcb910_0 .net "out", 7 0, L_0x55cf9dc33480; alias, 1 drivers +L_0x55cf9dc333e0 .part L_0x55cf9dc33910, 8, 1; +L_0x55cf9dc33480 .part L_0x55cf9dc33910, 0, 8; +L_0x55cf9dc33570 .concat [ 8 1 0 0], v0x55cf9dbd5320_0, L_0x7fcf8ba88180; +L_0x55cf9dc336a0 .concat [ 8 1 0 0], v0x55cf9dbd37c0_0, L_0x7fcf8ba881c8; +L_0x55cf9dc337d0 .arith/sum 9, L_0x55cf9dc33570, L_0x55cf9dc336a0; +L_0x55cf9dc33910 .arith/sum 9, L_0x55cf9dc337d0, L_0x7fcf8ba88840; +S_0x55cf9dbbe5e0 .scope module, "And8_23" "TC_And" 4 38, 6 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in0"; + .port_info 1 /INPUT 8 "in1"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9db7aba0 .param/l "BIT_WIDTH" 0 6 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9db7abe0 .param/str "NAME" 0 6 3, "\000"; +P_0x55cf9db7ac20 .param/l "UUID" 0 6 2, C4<0001000111000100101111100010000111011100011110110010011011001000>; +L_0x55cf9dc34270 .functor AND 8, v0x55cf9d9b4d60_0, v0x55cf9d975290_0, C4<11111111>, C4<11111111>; +v0x55cf9db96760_0 .net "in0", 7 0, v0x55cf9d9b4d60_0; alias, 1 drivers +v0x55cf9dbad3d0_0 .net "in1", 7 0, v0x55cf9d975290_0; alias, 1 drivers +v0x55cf9dbad010_0 .net "out", 7 0, L_0x55cf9dc34270; alias, 1 drivers +S_0x55cf9dbc1c60 .scope module, "And_77" "TC_And" 4 92, 6 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "in0"; + .port_info 1 /INPUT 1 "in1"; + .port_info 2 /OUTPUT 1 "out"; +P_0x55cf9db7b880 .param/l "BIT_WIDTH" 0 6 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9db7b8c0 .param/str "NAME" 0 6 3, "\000"; +P_0x55cf9db7b900 .param/l "UUID" 0 6 2, C4<0001100000111010010000110110010010011110111110010001001100011011>; +L_0x55cf9dc479b0 .functor AND 1, L_0x55cf9dc47900, v0x55cf9db7bc10_0, C4<1>, C4<1>; +v0x55cf9dba85b0_0 .net "in0", 0 0, L_0x55cf9dc47900; alias, 1 drivers +v0x55cf9db98350_0 .net "in1", 0 0, v0x55cf9db7bc10_0; alias, 1 drivers +v0x55cf9db97f70_0 .net "out", 0 0, L_0x55cf9dc479b0; alias, 1 drivers +S_0x55cf9dbc2010 .scope module, "Ashr8_32" "TC_Ashr" 4 47, 7 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /INPUT 8 "shift"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9db7c560 .param/l "BIT_WIDTH" 0 7 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9db7c5a0 .param/str "NAME" 0 7 3, "\000"; +P_0x55cf9db7c5e0 .param/l "UUID" 0 7 2, C4<0001010100100100100011100001000001111100010001100111000010000011>; +v0x55cf9db97340_0 .net "in", 7 0, v0x55cf9dbd99f0_0; alias, 1 drivers +v0x55cf9db96f30_0 .net "out", 7 0, L_0x55cf9dc34dd0; alias, 1 drivers +v0x55cf9db96b20_0 .net "shift", 7 0, v0x55cf9dbd91d0_0; alias, 1 drivers +L_0x55cf9dc34dd0 .shift/r 8, v0x55cf9dbd99f0_0, v0x55cf9dbd91d0_0; +S_0x55cf9dbb0bb0 .scope module, "Constant8_80" "TC_Constant" 4 95, 8 2 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /OUTPUT 8 "out"; +P_0x55cf9db95d70 .param/l "BIT_WIDTH" 0 8 5, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9db95db0 .param/str "NAME" 0 8 4, "\000"; +P_0x55cf9db95df0 .param/l "UUID" 0 8 3, C4<0011110111100011000001101100110010000101110010101000100100100100>; +P_0x55cf9db95e30 .param/l "value" 0 8 6, C4<10101010>; +v0x55cf9dba88f0_0 .net "out", 7 0, L_0x7fcf8ba88408; alias, 1 drivers +S_0x55cf9db900c0 .scope module, "Decoder3_1" "TC_Decoder3" 4 16, 9 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "dis"; + .port_info 1 /INPUT 1 "sel0"; + .port_info 2 /INPUT 1 "sel1"; + .port_info 3 /INPUT 1 "sel2"; + .port_info 4 /OUTPUT 1 "out0"; + .port_info 5 /OUTPUT 1 "out1"; + .port_info 6 /OUTPUT 1 "out2"; + .port_info 7 /OUTPUT 1 "out3"; + .port_info 8 /OUTPUT 1 "out4"; + .port_info 9 /OUTPUT 1 "out5"; + .port_info 10 /OUTPUT 1 "out6"; + .port_info 11 /OUTPUT 1 "out7"; +P_0x55cf9dbc4750 .param/str "NAME" 0 9 3, "\000"; +P_0x55cf9dbc4790 .param/l "UUID" 0 9 2, C4<0010010011000001101011001011110001000000110100100001101101110100>; +L_0x7fcf8ba88018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55cf9db8af80_0 .net "dis", 0 0, L_0x7fcf8ba88018; 1 drivers +v0x55cf9db52ea0_0 .var "out0", 0 0; +v0x55cf9db89ee0_0 .var "out1", 0 0; +v0x55cf9db87f80_0 .var "out2", 0 0; +v0x55cf9db87240_0 .var "out3", 0 0; +v0x55cf9db86500_0 .var "out4", 0 0; +v0x55cf9db83080_0 .var "out5", 0 0; +v0x55cf9db82370_0 .var "out6", 0 0; +v0x55cf9db81660_0 .var "out7", 0 0; +v0x55cf9db80950_0 .net "sel0", 0 0, L_0x55cf9dc329f0; alias, 1 drivers +v0x55cf9db7fc70_0 .net "sel1", 0 0, L_0x55cf9dc32950; alias, 1 drivers +v0x55cf9db7ef90_0 .net "sel2", 0 0, L_0x55cf9dc32870; alias, 1 drivers +E_0x55cf9d9d07d0 .event anyedge, v0x55cf9db80950_0, v0x55cf9db7fc70_0, v0x55cf9db7ef90_0, v0x55cf9db8af80_0; +S_0x55cf9db90440 .scope module, "Decoder3_27" "TC_Decoder3" 4 42, 9 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "dis"; + .port_info 1 /INPUT 1 "sel0"; + .port_info 2 /INPUT 1 "sel1"; + .port_info 3 /INPUT 1 "sel2"; + .port_info 4 /OUTPUT 1 "out0"; + .port_info 5 /OUTPUT 1 "out1"; + .port_info 6 /OUTPUT 1 "out2"; + .port_info 7 /OUTPUT 1 "out3"; + .port_info 8 /OUTPUT 1 "out4"; + .port_info 9 /OUTPUT 1 "out5"; + .port_info 10 /OUTPUT 1 "out6"; + .port_info 11 /OUTPUT 1 "out7"; +P_0x55cf9db52f60 .param/str "NAME" 0 9 3, "\000"; +P_0x55cf9db52fa0 .param/l "UUID" 0 9 2, C4<0001101101010010111011001011100010011000011101010101100110011110>; +L_0x7fcf8ba88258 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55cf9db7d5d0_0 .net "dis", 0 0, L_0x7fcf8ba88258; 1 drivers +v0x55cf9db7c8f0_0 .var "out0", 0 0; +v0x55cf9db7bc10_0 .var "out1", 0 0; +v0x55cf9db7af30_0 .var "out2", 0 0; +v0x55cf9db7afd0_0 .var "out3", 0 0; +v0x55cf9db7a250_0 .var "out4", 0 0; +v0x55cf9db7a2f0_0 .var "out5", 0 0; +v0x55cf9db79540_0 .var "out6", 0 0; +v0x55cf9db78830_0 .var "out7", 0 0; +v0x55cf9db77af0_0 .net "sel0", 0 0, L_0x55cf9dc327d0; alias, 1 drivers +v0x55cf9db76db0_0 .net "sel1", 0 0, L_0x55cf9dc326a0; alias, 1 drivers +v0x55cf9db760d0_0 .net "sel2", 0 0, L_0x55cf9dc32600; alias, 1 drivers +E_0x55cf9d9495c0 .event anyedge, v0x55cf9db77af0_0, v0x55cf9db76db0_0, v0x55cf9db760d0_0, v0x55cf9db7d5d0_0; +S_0x55cf9db962f0 .scope module, "DivMod8_78" "TC_Mul" 4 93, 10 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in0"; + .port_info 1 /INPUT 8 "in1"; + .port_info 2 /OUTPUT 8 "out0"; + .port_info 3 /OUTPUT 8 "out1"; +P_0x55cf9db7d240 .param/l "BIT_WIDTH" 0 10 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9db7d280 .param/str "NAME" 0 10 3, "\000"; +P_0x55cf9db7d2c0 .param/l "UUID" 0 10 2, C4<0001101000010101000010101111101001011000000111010101001111110111>; +v0x55cf9db753f0_0 .net "in0", 7 0, v0x55cf9dbdc710_0; alias, 1 drivers +v0x55cf9db746e0_0 .net "in1", 7 0, L_0x7fcf8ba88408; alias, 1 drivers +v0x55cf9db739d0_0 .net "out0", 7 0, L_0x55cf9dc47b80; alias, 1 drivers +v0x55cf9db4e6c0_0 .net "out1", 7 0, L_0x55cf9dc47cd0; alias, 1 drivers +L_0x55cf9dc47b80 .arith/div 8, v0x55cf9dbdc710_0, L_0x7fcf8ba88408; +L_0x55cf9dc47cd0 .arith/mod 8, v0x55cf9dbdc710_0, L_0x7fcf8ba88408; +S_0x55cf9dbcd5a0 .scope module, "Mul8_31" "TC_Mul" 4 46, 10 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in0"; + .port_info 1 /INPUT 8 "in1"; + .port_info 2 /OUTPUT 8 "out0"; + .port_info 3 /OUTPUT 8 "out1"; +P_0x55cf9db7df20 .param/l "BIT_WIDTH" 0 10 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9db7df60 .param/str "NAME" 0 10 3, "\000"; +P_0x55cf9db7dfa0 .param/l "UUID" 0 10 2, C4<0010111010110001000101010110110011101100011001000101011010010011>; +v0x55cf9db71fe0_0 .net "in0", 7 0, v0x55cf9dbdd900_0; alias, 1 drivers +v0x55cf9db71300_0 .net "in1", 7 0, v0x55cf9dbdcf80_0; alias, 1 drivers +v0x55cf9db70620_0 .net "out0", 7 0, L_0x55cf9dc34b70; alias, 1 drivers +v0x55cf9db6f910_0 .net "out1", 7 0, L_0x55cf9dc34c10; alias, 1 drivers +L_0x55cf9dc34b70 .arith/div 8, v0x55cf9dbdd900_0, v0x55cf9dbdcf80_0; +L_0x55cf9dc34c10 .arith/mod 8, v0x55cf9dbdd900_0, v0x55cf9dbdcf80_0; +S_0x55cf9dbc49d0 .scope module, "Nand8_26" "TC_Nand" 4 41, 11 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in0"; + .port_info 1 /INPUT 8 "in1"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9db7ec00 .param/l "BIT_WIDTH" 0 11 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9db7ec40 .param/str "NAME" 0 11 3, "\000"; +P_0x55cf9db7ec80 .param/l "UUID" 0 11 2, C4<0001100001011110101011011101011101101000101101011010000000100110>; +L_0x55cf9dc34790 .functor AND 8, v0x55cf9da38680_0, v0x55cf9d9a6e90_0, C4<11111111>, C4<11111111>; +L_0x55cf9dc34920 .functor NOT 8, L_0x55cf9dc34790, C4<00000000>, C4<00000000>, C4<00000000>; +v0x55cf9db6df70_0 .net *"_ivl_0", 7 0, L_0x55cf9dc34790; 1 drivers +v0x55cf9db6d240_0 .net "in0", 7 0, v0x55cf9da38680_0; alias, 1 drivers +v0x55cf9db6c560_0 .net "in1", 7 0, v0x55cf9d9a6e90_0; alias, 1 drivers +v0x55cf9db6b850_0 .net "out", 7 0, L_0x55cf9dc34920; alias, 1 drivers +S_0x55cf9dbc4d80 .scope module, "Neg8_33" "TC_Neg" 4 48, 12 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /OUTPUT 8 "out"; +P_0x55cf9db4da90 .param/l "BIT_WIDTH" 0 12 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9db4dad0 .param/str "NAME" 0 12 3, "\000"; +P_0x55cf9db4db10 .param/l "UUID" 0 12 2, C4<0010011000001110111110110001001100100100100101000110011011011100>; +L_0x7fcf8ba882a0 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v0x55cf9db69d80_0 .net/2u *"_ivl_0", 7 0, L_0x7fcf8ba882a0; 1 drivers +v0x55cf9db5d8d0_0 .net "in", 7 0, v0x55cf9dbdab70_0; alias, 1 drivers +v0x55cf9db5cbc0_0 .net "out", 7 0, L_0x55cf9dc34e70; alias, 1 drivers +L_0x55cf9dc34e70 .arith/sub 8, L_0x7fcf8ba882a0, v0x55cf9dbdab70_0; +S_0x55cf9dbc50d0 .scope module, "Neg8_6" "TC_Neg" 4 21, 12 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /OUTPUT 8 "out"; +P_0x55cf9db5beb0 .param/l "BIT_WIDTH" 0 12 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9db5bef0 .param/str "NAME" 0 12 3, "\000"; +P_0x55cf9db5bf30 .param/l "UUID" 0 12 2, C4<0001010101000110110111011010010001001111100000000111000110110000>; +L_0x7fcf8ba88138 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v0x55cf9db5b210_0 .net/2u *"_ivl_0", 7 0, L_0x7fcf8ba88138; 1 drivers +v0x55cf9db5a460_0 .net "in", 7 0, v0x55cf9dbea230_0; alias, 1 drivers +v0x55cf9db58a10_0 .net "out", 7 0, L_0x55cf9dc332d0; alias, 1 drivers +L_0x55cf9dc332d0 .arith/sub 8, L_0x7fcf8ba88138, v0x55cf9dbea230_0; +S_0x55cf9db8f540 .scope module, "Nor8_24" "TC_Nor" 4 39, 13 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in0"; + .port_info 1 /INPUT 8 "in1"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9db57d00 .param/l "BIT_WIDTH" 0 13 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9db57d40 .param/str "NAME" 0 13 3, "\000"; +P_0x55cf9db57d80 .param/l "UUID" 0 13 2, C4<0010101001110100010001001101011010111011010001101001001011011101>; +L_0x55cf9dc34400 .functor OR 8, v0x55cf9da2bb00_0, v0x55cf9da2e240_0, C4<00000000>, C4<00000000>; +L_0x55cf9dc34590 .functor NOT 8, L_0x55cf9dc34400, C4<00000000>, C4<00000000>, C4<00000000>; +v0x55cf9db56300_0 .net *"_ivl_0", 7 0, L_0x55cf9dc34400; 1 drivers +v0x55cf9db555a0_0 .net "in0", 7 0, v0x55cf9da2bb00_0; alias, 1 drivers +v0x55cf9db54890_0 .net "in1", 7 0, v0x55cf9da2e240_0; alias, 1 drivers +v0x55cf9db53b80_0 .net "out", 7 0, L_0x55cf9dc34590; alias, 1 drivers +S_0x55cf9db8d1d0 .scope module, "Not8_30" "TC_Not" 4 45, 14 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /OUTPUT 8 "out"; +P_0x55cf9db84a90 .param/l "BIT_WIDTH" 0 14 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9db84ad0 .param/str "NAME" 0 14 3, "\000"; +P_0x55cf9db84b10 .param/l "UUID" 0 14 2, C4<0001110110110010101100101100100111010011001100111111010111010100>; +L_0x55cf9dc34b00 .functor NOT 8, v0x55cf9dbd7fa0_0, C4<00000000>, C4<00000000>, C4<00000000>; +v0x55cf9db85790_0 .net "in", 7 0, v0x55cf9dbd7fa0_0; alias, 1 drivers +v0x55cf9dbad740_0 .net "out", 7 0, L_0x55cf9dc34b00; alias, 1 drivers +S_0x55cf9db95240 .scope module, "Or8_25" "TC_Or" 4 40, 15 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in0"; + .port_info 1 /INPUT 8 "in1"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9db628c0 .param/l "BIT_WIDTH" 0 15 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9db62900 .param/str "NAME" 0 15 3, "\000"; +P_0x55cf9db62940 .param/l "UUID" 0 15 2, C4<0011110011001010001111010100001111101110110101011010011111101100>; +L_0x55cf9dc34600 .functor OR 8, v0x55cf9d9a4010_0, v0x55cf9da1fe30_0, C4<00000000>, C4<00000000>; +v0x55cf9db8cd00_0 .net "in0", 7 0, v0x55cf9d9a4010_0; alias, 1 drivers +v0x55cf9db641a0_0 .net "in1", 7 0, v0x55cf9da1fe30_0; alias, 1 drivers +v0x55cf9dabd780_0 .net "out", 7 0, L_0x55cf9dc34600; alias, 1 drivers +S_0x55cf9dbaaa90 .scope module, "Or_76" "TC_Or" 4 91, 15 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "in0"; + .port_info 1 /INPUT 1 "in1"; + .port_info 2 /OUTPUT 1 "out"; +P_0x55cf9dabd360 .param/l "BIT_WIDTH" 0 15 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dabd3a0 .param/str "NAME" 0 15 3, "\000"; +P_0x55cf9dabd3e0 .param/l "UUID" 0 15 2, C4<0011000001100000111101101001010010100100100111111110000111011110>; +L_0x55cf9dc47900 .functor OR 1, v0x55cf9db89ee0_0, v0x55cf9db87f80_0, C4<0>, C4<0>; +v0x55cf9dbb9c00_0 .net "in0", 0 0, v0x55cf9db89ee0_0; alias, 1 drivers +v0x55cf9dbb6580_0 .net "in1", 0 0, v0x55cf9db87f80_0; alias, 1 drivers +v0x55cf9dbb6650_0 .net "out", 0 0, L_0x55cf9dc47900; alias, 1 drivers +S_0x55cf9dba30d0 .scope module, "Output8z_72" "TC_Switch" 4 87, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbb2f00 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbb2f40 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbb2f80 .param/l "UUID" 0 16 2, C4<0010011011111000001000111100100101111110110010001001001110000001>; +v0x55cf9db8b2a0_0 .net "en", 0 0, L_0x55cf9dc479b0; alias, 1 drivers +v0x55cf9db4ce90_0 .net "in", 7 0, L_0x55cf9dc49280; alias, 1 drivers +v0x55cf9db4cf50_0 .net "out", 7 0, v0x55cf9db59750_0; alias, 1 drivers +v0x55cf9db59750_0 .var "outval", 7 0; +E_0x55cf9db556b0 .event anyedge, v0x55cf9db4ce90_0, v0x55cf9db97f70_0; +S_0x55cf9dbca640 .scope module, "Rol8_34" "TC_Rol" 4 49, 17 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /INPUT 8 "shift"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dba46a0 .param/l "BIT_WIDTH" 0 17 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dba46e0 .param/str "NAME" 0 17 3, "\000"; +P_0x55cf9dba4720 .param/l "UUID" 0 17 2, C4<0011110111001100110110000011001100110101010110111101101101010100>; +L_0x55cf9dc34f10 .functor OR 8, L_0x55cf9dc34f80, L_0x55cf9dc45200, C4<00000000>, C4<00000000>; +v0x55cf9dbc8540_0 .net *"_ivl_0", 7 0, L_0x55cf9dc34f80; 1 drivers +v0x55cf9dbc8640_0 .net *"_ivl_10", 7 0, L_0x55cf9dc45200; 1 drivers +L_0x7fcf8ba882e8 .functor BUFT 1, C4<0000000000000000000000000000000000000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x55cf9dbc7d00_0 .net/2u *"_ivl_2", 63 0, L_0x7fcf8ba882e8; 1 drivers +v0x55cf9dbc7dd0_0 .net *"_ivl_4", 63 0, L_0x55cf9dc45030; 1 drivers +L_0x7fcf8ba88330 .functor BUFT 1, C4<00000000000000000000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55cf9dbc74e0_0 .net *"_ivl_7", 55 0, L_0x7fcf8ba88330; 1 drivers +v0x55cf9dbc9e00_0 .net *"_ivl_8", 63 0, L_0x55cf9dc45160; 1 drivers +v0x55cf9dbc9ee0_0 .net "in", 7 0, v0x55cf9dbe0f20_0; alias, 1 drivers +v0x55cf9dbc95c0_0 .net "out", 7 0, L_0x55cf9dc34f10; alias, 1 drivers +v0x55cf9dbc96a0_0 .net "shift", 7 0, v0x55cf9dbe06c0_0; alias, 1 drivers +L_0x55cf9dc34f80 .shift/r 8, v0x55cf9dbe0f20_0, v0x55cf9dbe06c0_0; +L_0x55cf9dc45030 .concat [ 8 56 0 0], v0x55cf9dbe06c0_0, L_0x7fcf8ba88330; +L_0x55cf9dc45160 .arith/sub 64, L_0x7fcf8ba882e8, L_0x55cf9dc45030; +L_0x55cf9dc45200 .shift/l 8, v0x55cf9dbe0f20_0, L_0x55cf9dc45160; +S_0x55cf9db8f030 .scope module, "Ror8_35" "TC_Ror" 4 50, 18 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /INPUT 8 "shift"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9db8fc30 .param/l "BIT_WIDTH" 0 18 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9db8fc70 .param/str "NAME" 0 18 3, "\000"; +P_0x55cf9db8fcb0 .param/l "UUID" 0 18 2, C4<0010011001000110111100110010101000010010100101101100101111010101>; +L_0x55cf9dc455a0 .functor OR 8, L_0x55cf9dc45330, L_0x55cf9dc45610, C4<00000000>, C4<00000000>; +v0x55cf9db8c900_0 .net *"_ivl_0", 7 0, L_0x55cf9dc45330; 1 drivers +v0x55cf9db68cf0_0 .net *"_ivl_10", 7 0, L_0x55cf9dc45610; 1 drivers +L_0x7fcf8ba88378 .functor BUFT 1, C4<0000000000000000000000000000000000000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x55cf9db68dd0_0 .net/2u *"_ivl_2", 63 0, L_0x7fcf8ba88378; 1 drivers +v0x55cf9db66e60_0 .net *"_ivl_4", 63 0, L_0x55cf9dc453d0; 1 drivers +L_0x7fcf8ba883c0 .functor BUFT 1, C4<00000000000000000000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55cf9db66f40_0 .net *"_ivl_7", 55 0, L_0x7fcf8ba883c0; 1 drivers +v0x55cf9db5ed10_0 .net *"_ivl_8", 63 0, L_0x55cf9dc45500; 1 drivers +v0x55cf9db5edd0_0 .net "in", 7 0, v0x55cf9dbe2630_0; alias, 1 drivers +v0x55cf9db4f680_0 .net "out", 7 0, L_0x55cf9dc455a0; alias, 1 drivers +v0x55cf9db4f760_0 .net "shift", 7 0, v0x55cf9dbe18a0_0; alias, 1 drivers +L_0x55cf9dc45330 .shift/l 8, v0x55cf9dbe2630_0, v0x55cf9dbe18a0_0; +L_0x55cf9dc453d0 .concat [ 8 56 0 0], v0x55cf9dbe18a0_0, L_0x7fcf8ba883c0; +L_0x55cf9dc45500 .arith/sub 64, L_0x7fcf8ba88378, L_0x55cf9dc453d0; +L_0x55cf9dc45610 .shift/r 8, v0x55cf9dbe2630_0, L_0x55cf9dc45500; +S_0x55cf9db5f9b0 .scope module, "Shl8_37" "TC_Shl" 4 52, 19 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /INPUT 8 "shift"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9db65110 .param/l "BIT_WIDTH" 0 19 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9db65150 .param/str "NAME" 0 19 3, "\000"; +P_0x55cf9db65190 .param/l "UUID" 0 19 2, C4<0011000110110011010111110011110010101001001111010111000010000111>; +v0x55cf9dbbb360_0 .net "in", 7 0, v0x55cf9dbe3f70_0; alias, 1 drivers +v0x55cf9dbb7c90_0 .net "out", 7 0, L_0x55cf9dc45880; alias, 1 drivers +v0x55cf9dbb7d70_0 .net "shift", 7 0, v0x55cf9dbe3710_0; alias, 1 drivers +L_0x55cf9dc45880 .shift/l 8, v0x55cf9dbe3f70_0, v0x55cf9dbe3710_0; +S_0x55cf9dbb4610 .scope module, "Shr8_36" "TC_Shr" 4 51, 20 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /INPUT 8 "shift"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9da7cce0 .param/l "BIT_WIDTH" 0 20 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9da7cd20 .param/str "NAME" 0 20 3, "\000"; +P_0x55cf9da7cd60 .param/l "UUID" 0 20 2, C4<0001101110000110100000001100010100010000010110111000100110010100>; +v0x55cf9da76380_0 .net "in", 7 0, v0x55cf9dbe2ea0_0; alias, 1 drivers +v0x55cf9da76480_0 .net "out", 7 0, L_0x55cf9dc457e0; alias, 1 drivers +v0x55cf9da76560_0 .net "shift", 7 0, v0x55cf9dbe47e0_0; alias, 1 drivers +L_0x55cf9dc457e0 .shift/r 8, v0x55cf9dbe2ea0_0, v0x55cf9dbe47e0_0; +S_0x55cf9d94ee30 .scope module, "Splitter8_0" "TC_Splitter8" 4 15, 21 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /OUTPUT 1 "out0"; + .port_info 2 /OUTPUT 1 "out1"; + .port_info 3 /OUTPUT 1 "out2"; + .port_info 4 /OUTPUT 1 "out3"; + .port_info 5 /OUTPUT 1 "out4"; + .port_info 6 /OUTPUT 1 "out5"; + .port_info 7 /OUTPUT 1 "out6"; + .port_info 8 /OUTPUT 1 "out7"; +P_0x55cf9db82430 .param/str "NAME" 0 21 3, "\000"; +P_0x55cf9db82470 .param/l "UUID" 0 21 2, C4<0011011111010000111111110011010000010010110101011000000010111010>; +L_0x55cf9dc32ae0 .functor BUFZ 8, L_0x55cf9dc48da0, C4<00000000>, C4<00000000>, C4<00000000>; +v0x55cf9d94f150_0 .net *"_ivl_10", 7 0, L_0x55cf9dc32ae0; 1 drivers +v0x55cf9da766a0_0 .net "in", 7 0, L_0x55cf9dc48da0; alias, 1 drivers +v0x55cf9da64290_0 .net "out0", 0 0, L_0x55cf9dc329f0; alias, 1 drivers +v0x55cf9da64330_0 .net "out1", 0 0, L_0x55cf9dc32950; alias, 1 drivers +v0x55cf9da64400_0 .net "out2", 0 0, L_0x55cf9dc32870; alias, 1 drivers +v0x55cf9da644f0_0 .net "out3", 0 0, L_0x55cf9dc327d0; alias, 1 drivers +v0x55cf9da645c0_0 .net "out4", 0 0, L_0x55cf9dc326a0; alias, 1 drivers +v0x55cf9da07a70_0 .net "out5", 0 0, L_0x55cf9dc32600; alias, 1 drivers +v0x55cf9da07b40_0 .net "out6", 0 0, L_0x55cf9dc32560; 1 drivers +v0x55cf9da07be0_0 .net "out7", 0 0, L_0x55cf9dc324c0; 1 drivers +L_0x55cf9dc324c0 .part L_0x55cf9dc32ae0, 7, 1; +L_0x55cf9dc32560 .part L_0x55cf9dc32ae0, 6, 1; +L_0x55cf9dc32600 .part L_0x55cf9dc32ae0, 5, 1; +L_0x55cf9dc326a0 .part L_0x55cf9dc32ae0, 4, 1; +L_0x55cf9dc327d0 .part L_0x55cf9dc32ae0, 3, 1; +L_0x55cf9dc32870 .part L_0x55cf9dc32ae0, 2, 1; +L_0x55cf9dc32950 .part L_0x55cf9dc32ae0, 1, 1; +L_0x55cf9dc329f0 .part L_0x55cf9dc32ae0, 0, 1; +S_0x55cf9da07d00 .scope module, "Switch1_70" "TC_Switch" 4 85, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 1 "in"; + .port_info 2 /OUTPUT 1 "out"; +P_0x55cf9d96eda0 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9d96ede0 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9d96ee20 .param/l "UUID" 0 16 2, C4<0010000100101101110000010101111111110011010011111111101000011000>; +v0x55cf9d96f0d0_0 .net "en", 0 0, v0x55cf9db86500_0; alias, 1 drivers +v0x55cf9da26e50_0 .net "in", 0 0, L_0x55cf9dc333e0; alias, 1 drivers +v0x55cf9da26f20_0 .net "out", 0 0, v0x55cf9da26ff0_0; alias, 1 drivers +v0x55cf9da26ff0_0 .var "outval", 0 0; +E_0x55cf9db563c0 .event anyedge, v0x55cf9dbcd280_0, v0x55cf9db86500_0; +S_0x55cf9da44c70 .scope module, "Switch1_71" "TC_Switch" 4 86, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 1 "in"; + .port_info 2 /OUTPUT 1 "out"; +P_0x55cf9da44e50 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9da44e90 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9da44ed0 .param/l "UUID" 0 16 2, C4<0000100100000111100001010111000110010111011000100010010100110111>; +v0x55cf9da27150_0 .net "en", 0 0, v0x55cf9db87240_0; alias, 1 drivers +v0x55cf9da211b0_0 .net "in", 0 0, L_0x55cf9dc32b50; alias, 1 drivers +v0x55cf9da21280_0 .net "out", 0 0, v0x55cf9da21350_0; alias, 1 drivers +v0x55cf9da21350_0 .var "outval", 0 0; +E_0x55cf9db6c670 .event anyedge, v0x55cf9dbbac70_0, v0x55cf9db87240_0; +S_0x55cf9da42e60 .scope module, "Switch8_10" "TC_Switch" 4 25, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9da43040 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9da43080 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9da430c0 .param/l "UUID" 0 16 2, C4<0001001110000111111000011000000011100001000100011110111000001000>; +v0x55cf9da214b0_0 .net "en", 0 0, v0x55cf9db87240_0; alias, 1 drivers +v0x55cf9da759d0_0 .net "in", 7 0, L_0x55cf9dc32bf0; alias, 1 drivers +v0x55cf9da75a90_0 .net "out", 7 0, v0x55cf9da75b60_0; alias, 1 drivers +v0x55cf9da75b60_0 .var "outval", 7 0; +E_0x55cf9da432a0 .event anyedge, v0x55cf9dbb72d0_0, v0x55cf9db87240_0; +S_0x55cf9da75cc0 .scope module, "Switch8_11" "TC_Switch" 4 26, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9da04d70 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9da04db0 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9da04df0 .param/l "UUID" 0 16 2, C4<0011111101111001100100110110000010011111111100011101011000110000>; +v0x55cf9da050c0_0 .net "en", 0 0, v0x55cf9db52ea0_0; alias, 1 drivers +v0x55cf9d9a3e50_0 .net "in", 7 0, L_0x55cf9dc47f80; alias, 1 drivers +v0x55cf9d9a3f10_0 .net "out", 7 0, v0x55cf9d9a4010_0; alias, 1 drivers +v0x55cf9d9a4010_0 .var "outval", 7 0; +E_0x55cf9da05040 .event anyedge, v0x55cf9d9a3e50_0, v0x55cf9db52ea0_0; +S_0x55cf9d9a8f20 .scope module, "Switch8_12" "TC_Switch" 4 27, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9d9a9100 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9d9a9140 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9d9a9180 .param/l "UUID" 0 16 2, C4<0011110111011101101010111000011111111100010011101110110011000101>; +v0x55cf9d9a4150_0 .net "en", 0 0, v0x55cf9db52ea0_0; alias, 1 drivers +v0x55cf9da1fc80_0 .net "in", 7 0, L_0x55cf9dc47ef0; alias, 1 drivers +v0x55cf9da1fd60_0 .net "out", 7 0, v0x55cf9da1fe30_0; alias, 1 drivers +v0x55cf9da1fe30_0 .var "outval", 7 0; +E_0x55cf9d9a9360 .event anyedge, v0x55cf9da1fc80_0, v0x55cf9db52ea0_0; +S_0x55cf9da1ff70 .scope module, "Switch8_13" "TC_Switch" 4 28, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9d975730 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9d975770 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9d9757b0 .param/l "UUID" 0 16 2, C4<0001010011100001011101001010100010111111001000100000111000111000>; +v0x55cf9d975a60_0 .net "en", 0 0, v0x55cf9db52ea0_0; alias, 1 drivers +v0x55cf9d94b500_0 .net "in", 7 0, L_0x55cf9dc34600; alias, 1 drivers +v0x55cf9d94b5f0_0 .net "out", 7 0, v0x55cf9d94b6c0_0; alias, 1 drivers +v0x55cf9d94b6c0_0 .var "outval", 7 0; +E_0x55cf9d9759e0 .event anyedge, v0x55cf9dabd780_0, v0x55cf9db52ea0_0; +S_0x55cf9d96e360 .scope module, "Switch8_14" "TC_Switch" 4 29, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9d96e540 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9d96e580 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9d96e5c0 .param/l "UUID" 0 16 2, C4<0011110000000010001001000100011000011010100011000001110111001111>; +v0x55cf9d94b820_0 .net "en", 0 0, v0x55cf9db89ee0_0; alias, 1 drivers +v0x55cf9d9a6d30_0 .net "in", 7 0, L_0x55cf9dc47ef0; alias, 1 drivers +v0x55cf9d9a6df0_0 .net "out", 7 0, v0x55cf9d9a6e90_0; alias, 1 drivers +v0x55cf9d9a6e90_0 .var "outval", 7 0; +E_0x55cf9da27240 .event anyedge, v0x55cf9da1fc80_0, v0x55cf9db89ee0_0; +S_0x55cf9d9a6fb0 .scope module, "Switch8_15" "TC_Switch" 4 30, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9d970d30 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9d970d70 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9d970db0 .param/l "UUID" 0 16 2, C4<0010010011110110110111010001101111111110101111101001111011011101>; +v0x55cf9d971080_0 .net "en", 0 0, v0x55cf9db89ee0_0; alias, 1 drivers +v0x55cf9da38490_0 .net "in", 7 0, L_0x55cf9dc47f80; alias, 1 drivers +v0x55cf9da38580_0 .net "out", 7 0, v0x55cf9da38680_0; alias, 1 drivers +v0x55cf9da38680_0 .var "outval", 7 0; +E_0x55cf9d971000 .event anyedge, v0x55cf9d9a3e50_0, v0x55cf9db89ee0_0; +S_0x55cf9d9aabb0 .scope module, "Switch8_16" "TC_Switch" 4 31, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9d9aad90 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9d9aadd0 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9d9aae10 .param/l "UUID" 0 16 2, C4<0010111100111101000011000011001001110000110111011111111011101001>; +v0x55cf9da387a0_0 .net "en", 0 0, v0x55cf9db89ee0_0; alias, 1 drivers +v0x55cf9da38860_0 .net "in", 7 0, L_0x55cf9dc34920; alias, 1 drivers +v0x55cf9da20900_0 .net "out", 7 0, v0x55cf9da209f0_0; alias, 1 drivers +v0x55cf9da209f0_0 .var "outval", 7 0; +E_0x55cf9d971140 .event anyedge, v0x55cf9db6b850_0, v0x55cf9db89ee0_0; +S_0x55cf9da20b50 .scope module, "Switch8_17" "TC_Switch" 4 32, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9da63850 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9da63890 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9da638d0 .param/l "UUID" 0 16 2, C4<0011111111010100001101010010110101011010010000100100100011010110>; +v0x55cf9da20ce0_0 .net "en", 0 0, v0x55cf9db87f80_0; alias, 1 drivers +v0x55cf9da63c10_0 .net "in", 7 0, L_0x55cf9dc47f80; alias, 1 drivers +v0x55cf9da2ba60_0 .net "out", 7 0, v0x55cf9da2bb00_0; alias, 1 drivers +v0x55cf9da2bb00_0 .var "outval", 7 0; +E_0x55cf9da63b20 .event anyedge, v0x55cf9d9a3e50_0, v0x55cf9db87f80_0; +S_0x55cf9da2bc40 .scope module, "Switch8_18" "TC_Switch" 4 33, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9da30330 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9da30370 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9da303b0 .param/l "UUID" 0 16 2, C4<0011011100001110000001011000011110111011101111110100011010001110>; +v0x55cf9da30680_0 .net "en", 0 0, v0x55cf9db87f80_0; alias, 1 drivers +v0x55cf9da2be20_0 .net "in", 7 0, L_0x55cf9dc47ef0; alias, 1 drivers +v0x55cf9da2e1a0_0 .net "out", 7 0, v0x55cf9da2e240_0; alias, 1 drivers +v0x55cf9da2e240_0 .var "outval", 7 0; +E_0x55cf9da30600 .event anyedge, v0x55cf9da1fc80_0, v0x55cf9db87f80_0; +S_0x55cf9da2e360 .scope module, "Switch8_19" "TC_Switch" 4 34, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9da2e540 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9da2e580 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9da2e5c0 .param/l "UUID" 0 16 2, C4<0010010110001011011100000010010010111110001110000110000000110101>; +v0x55cf9da40930_0 .net "en", 0 0, v0x55cf9db87f80_0; alias, 1 drivers +v0x55cf9da409f0_0 .net "in", 7 0, L_0x55cf9dc34590; alias, 1 drivers +v0x55cf9d9b4240_0 .net "out", 7 0, v0x55cf9d9b4310_0; alias, 1 drivers +v0x55cf9d9b4310_0 .var "outval", 7 0; +E_0x55cf9da408b0 .event anyedge, v0x55cf9db53b80_0, v0x55cf9db87f80_0; +S_0x55cf9d9b4470 .scope module, "Switch8_20" "TC_Switch" 4 35, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9d94e500 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9d94e540 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9d94e580 .param/l "UUID" 0 16 2, C4<0010100100101111101100111100101010100101110010001011101000010100>; +v0x55cf9d94e800_0 .net "en", 0 0, v0x55cf9db87240_0; alias, 1 drivers +v0x55cf9d9b4600_0 .net "in", 7 0, L_0x55cf9dc47ef0; alias, 1 drivers +v0x55cf9d94e8c0_0 .net "out", 7 0, v0x55cf9d975290_0; alias, 1 drivers +v0x55cf9d975290_0 .var "outval", 7 0; +E_0x55cf9d94e780 .event anyedge, v0x55cf9da1fc80_0, v0x55cf9db87240_0; +S_0x55cf9d9753b0 .scope module, "Switch8_21" "TC_Switch" 4 36, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9d975590 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9d9755d0 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9d975610 .param/l "UUID" 0 16 2, C4<0011000010001110001010000111100100010010001011011110010111010000>; +v0x55cf9da22bb0_0 .net "en", 0 0, v0x55cf9db87240_0; alias, 1 drivers +v0x55cf9da22d00_0 .net "in", 7 0, L_0x55cf9dc47f80; alias, 1 drivers +v0x55cf9d9b4c60_0 .net "out", 7 0, v0x55cf9d9b4d60_0; alias, 1 drivers +v0x55cf9d9b4d60_0 .var "outval", 7 0; +E_0x55cf9da22b30 .event anyedge, v0x55cf9d9a3e50_0, v0x55cf9db87240_0; +S_0x55cf9d9b4ea0 .scope module, "Switch8_22" "TC_Switch" 4 37, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9da2a130 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9da2a170 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9da2a1b0 .param/l "UUID" 0 16 2, C4<0000111111011001111110000100011000110001110100110110001011011101>; +v0x55cf9da2a440_0 .net "en", 0 0, v0x55cf9db87240_0; alias, 1 drivers +v0x55cf9da2a500_0 .net "in", 7 0, L_0x55cf9dc34270; alias, 1 drivers +v0x55cf9d9b5030_0 .net "out", 7 0, v0x55cf9da25470_0; alias, 1 drivers +v0x55cf9da25470_0 .var "outval", 7 0; +E_0x55cf9da22dc0 .event anyedge, v0x55cf9dbad010_0, v0x55cf9db87240_0; +S_0x55cf9da255b0 .scope module, "Switch8_3" "TC_Switch" 4 18, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9da25790 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9da257d0 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9da25810 .param/l "UUID" 0 16 2, C4<0000100000011000111011111110001101001111001011100010000100111001>; +v0x55cf9d95e7b0_0 .net "en", 0 0, v0x55cf9db86500_0; alias, 1 drivers +v0x55cf9d95e8c0_0 .net "in", 7 0, L_0x55cf9dc47ef0; alias, 1 drivers +v0x55cf9d95ea10_0 .net "out", 7 0, v0x55cf9dbd37c0_0; alias, 1 drivers +v0x55cf9dbd37c0_0 .var "outval", 7 0; +E_0x55cf9d95e730 .event anyedge, v0x55cf9da1fc80_0, v0x55cf9db86500_0; +S_0x55cf9dbd3900 .scope module, "Switch8_38" "TC_Switch" 4 53, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbd3a90 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbd3ad0 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbd3b10 .param/l "UUID" 0 16 2, C4<0001000110111100011110000010101000011100100111111010101000101111>; +v0x55cf9dbd3de0_0 .net "en", 0 0, v0x55cf9db83080_0; alias, 1 drivers +v0x55cf9dbd3ed0_0 .net "in", 7 0, L_0x55cf9dc47ef0; alias, 1 drivers +v0x55cf9dbd3f70_0 .net "out", 7 0, v0x55cf9dbd4060_0; alias, 1 drivers +v0x55cf9dbd4060_0 .var "outval", 7 0; +E_0x55cf9dbd3d60 .event anyedge, v0x55cf9da1fc80_0, v0x55cf9db83080_0; +S_0x55cf9dbd41c0 .scope module, "Switch8_39" "TC_Switch" 4 54, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbd43a0 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbd43e0 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbd4420 .param/l "UUID" 0 16 2, C4<0001100110111001100011101110011010111001111110110001100100101101>; +v0x55cf9dbd46f0_0 .net "en", 0 0, v0x55cf9db83080_0; alias, 1 drivers +v0x55cf9dbd4800_0 .net "in", 7 0, L_0x55cf9dc47f80; alias, 1 drivers +v0x55cf9dbd4950_0 .net "out", 7 0, v0x55cf9dbd4a10_0; alias, 1 drivers +v0x55cf9dbd4a10_0 .var "outval", 7 0; +E_0x55cf9dbd4670 .event anyedge, v0x55cf9d9a3e50_0, v0x55cf9db83080_0; +S_0x55cf9dbd4b70 .scope module, "Switch8_4" "TC_Switch" 4 19, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbd4d50 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbd4d90 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbd4dd0 .param/l "UUID" 0 16 2, C4<0010000011000101010111101010011011010001110100001110110111011000>; +v0x55cf9dbd50a0_0 .net "en", 0 0, v0x55cf9db86500_0; alias, 1 drivers +v0x55cf9dbd5160_0 .net "in", 7 0, L_0x55cf9dc47f80; alias, 1 drivers +v0x55cf9dbd5220_0 .net "out", 7 0, v0x55cf9dbd5320_0; alias, 1 drivers +v0x55cf9dbd5320_0 .var "outval", 7 0; +E_0x55cf9dbd5020 .event anyedge, v0x55cf9d9a3e50_0, v0x55cf9db86500_0; +S_0x55cf9dbd5460 .scope module, "Switch8_40" "TC_Switch" 4 55, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbd5640 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbd5680 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbd56c0 .param/l "UUID" 0 16 2, C4<0001000010110100100110010011101111000010110101110100100111010110>; +v0x55cf9dbd5990_0 .net "en", 0 0, v0x55cf9db83080_0; alias, 1 drivers +v0x55cf9dbd5a50_0 .net "in", 7 0, L_0x55cf9dc34a90; alias, 1 drivers +v0x55cf9dbd5b30_0 .net "out", 7 0, v0x55cf9dbd5c20_0; alias, 1 drivers +v0x55cf9dbd5c20_0 .var "outval", 7 0; +E_0x55cf9dbd5910 .event anyedge, v0x55cf9dbd5a50_0, v0x55cf9db83080_0; +S_0x55cf9dbd5d80 .scope module, "Switch8_41" "TC_Switch" 4 56, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbd5f60 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbd5fa0 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbd5fe0 .param/l "UUID" 0 16 2, C4<0001010110011110010100111111001001111100100010111010101100111010>; +v0x55cf9dbd6230_0 .net "en", 0 0, v0x55cf9db86500_0; alias, 1 drivers +v0x55cf9dbd6380_0 .net "in", 7 0, L_0x55cf9dc47ef0; alias, 1 drivers +v0x55cf9dbd6440_0 .net "out", 7 0, v0x55cf9dbd6530_0; alias, 1 drivers +v0x55cf9dbd6530_0 .var "outval", 7 0; +S_0x55cf9dbd6690 .scope module, "Switch8_42" "TC_Switch" 4 57, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbd6820 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbd6860 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbd68a0 .param/l "UUID" 0 16 2, C4<0011110010111001100011010100100000110111000010001000110001000000>; +v0x55cf9dbd6af0_0 .net "en", 0 0, v0x55cf9db86500_0; alias, 1 drivers +v0x55cf9dbd6bb0_0 .net "in", 7 0, L_0x55cf9dc47f80; alias, 1 drivers +v0x55cf9dbd6c70_0 .net "out", 7 0, v0x55cf9dbd6d60_0; alias, 1 drivers +v0x55cf9dbd6d60_0 .var "outval", 7 0; +S_0x55cf9dbd6ec0 .scope module, "Switch8_43" "TC_Switch" 4 58, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbd70a0 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbd70e0 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbd7120 .param/l "UUID" 0 16 2, C4<0000101101100010001101101011010101011111000000011010101110001001>; +v0x55cf9dbd73f0_0 .net "en", 0 0, v0x55cf9db86500_0; alias, 1 drivers +v0x55cf9dbd74b0_0 .net "in", 7 0, L_0x55cf9dc34a20; alias, 1 drivers +v0x55cf9dbd7590_0 .net "out", 7 0, v0x55cf9dbd7680_0; alias, 1 drivers +v0x55cf9dbd7680_0 .var "outval", 7 0; +E_0x55cf9dbd7370 .event anyedge, v0x55cf9dbd74b0_0, v0x55cf9db86500_0; +S_0x55cf9dbd77e0 .scope module, "Switch8_44" "TC_Switch" 4 59, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbd79c0 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbd7a00 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbd7a40 .param/l "UUID" 0 16 2, C4<0011100000100011011110101000110101110101101110101111000011011111>; +v0x55cf9dbd7d10_0 .net "en", 0 0, v0x55cf9db82370_0; alias, 1 drivers +v0x55cf9dbd7e00_0 .net "in", 7 0, L_0x55cf9dc47f80; alias, 1 drivers +v0x55cf9dbd7ea0_0 .net "out", 7 0, v0x55cf9dbd7fa0_0; alias, 1 drivers +v0x55cf9dbd7fa0_0 .var "outval", 7 0; +E_0x55cf9dbd7c90 .event anyedge, v0x55cf9d9a3e50_0, v0x55cf9db82370_0; +S_0x55cf9dbd80e0 .scope module, "Switch8_45" "TC_Switch" 4 60, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbd82c0 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbd8300 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbd8340 .param/l "UUID" 0 16 2, C4<0000011011111010011100110000000000010011000110000100110010011010>; +v0x55cf9dbd8610_0 .net "en", 0 0, v0x55cf9db82370_0; alias, 1 drivers +v0x55cf9dbd8720_0 .net "in", 7 0, L_0x55cf9dc34b00; alias, 1 drivers +v0x55cf9dbd87e0_0 .net "out", 7 0, v0x55cf9dbd88b0_0; alias, 1 drivers +v0x55cf9dbd88b0_0 .var "outval", 7 0; +E_0x55cf9dbd8590 .event anyedge, v0x55cf9dbad740_0, v0x55cf9db82370_0; +S_0x55cf9dbd8a10 .scope module, "Switch8_46" "TC_Switch" 4 61, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbd8bf0 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbd8c30 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbd8c70 .param/l "UUID" 0 16 2, C4<0000100010100001110001100101111111101100000010011010100100001000>; +v0x55cf9dbd8ec0_0 .net "en", 0 0, v0x55cf9db52ea0_0; alias, 1 drivers +v0x55cf9dbd9010_0 .net "in", 7 0, L_0x55cf9dc47ef0; alias, 1 drivers +v0x55cf9dbd90d0_0 .net "out", 7 0, v0x55cf9dbd91d0_0; alias, 1 drivers +v0x55cf9dbd91d0_0 .var "outval", 7 0; +S_0x55cf9dbd9310 .scope module, "Switch8_47" "TC_Switch" 4 62, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbd94a0 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbd94e0 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbd9520 .param/l "UUID" 0 16 2, C4<0010111101010110101011111100101100000111011111010101011000110110>; +v0x55cf9dbd9770_0 .net "en", 0 0, v0x55cf9db52ea0_0; alias, 1 drivers +v0x55cf9dbd9830_0 .net "in", 7 0, L_0x55cf9dc47f80; alias, 1 drivers +v0x55cf9dbd98f0_0 .net "out", 7 0, v0x55cf9dbd99f0_0; alias, 1 drivers +v0x55cf9dbd99f0_0 .var "outval", 7 0; +S_0x55cf9dbd9b30 .scope module, "Switch8_48" "TC_Switch" 4 63, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbd9d10 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbd9d50 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbd9d90 .param/l "UUID" 0 16 2, C4<0000000001100010000110111101101110011001101100000000001001011101>; +v0x55cf9dbda060_0 .net "en", 0 0, v0x55cf9db52ea0_0; alias, 1 drivers +v0x55cf9dbda120_0 .net "in", 7 0, L_0x55cf9dc34dd0; alias, 1 drivers +v0x55cf9dbda210_0 .net "out", 7 0, v0x55cf9dbda2e0_0; alias, 1 drivers +v0x55cf9dbda2e0_0 .var "outval", 7 0; +E_0x55cf9dbd9fe0 .event anyedge, v0x55cf9db96f30_0, v0x55cf9db52ea0_0; +S_0x55cf9dbda440 .scope module, "Switch8_49" "TC_Switch" 4 64, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbda620 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbda660 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbda6a0 .param/l "UUID" 0 16 2, C4<0001011100100000100101101111001001100100101110110100010010100111>; +v0x55cf9dbda8f0_0 .net "en", 0 0, v0x55cf9db86500_0; alias, 1 drivers +v0x55cf9dbda9b0_0 .net "in", 7 0, L_0x55cf9dc47f80; alias, 1 drivers +v0x55cf9dbdaa70_0 .net "out", 7 0, v0x55cf9dbdab70_0; alias, 1 drivers +v0x55cf9dbdab70_0 .var "outval", 7 0; +S_0x55cf9dbdacb0 .scope module, "Switch8_5" "TC_Switch" 4 20, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbdae90 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbdaed0 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbdaf10 .param/l "UUID" 0 16 2, C4<0010110001001100000111000000011100001101010001011111011111000100>; +v0x55cf9dbdb1e0_0 .net "en", 0 0, v0x55cf9db86500_0; alias, 1 drivers +v0x55cf9dbdb2a0_0 .net "in", 7 0, L_0x55cf9dc33480; alias, 1 drivers +v0x55cf9dbdb390_0 .net "out", 7 0, v0x55cf9dbdb460_0; alias, 1 drivers +v0x55cf9dbdb460_0 .var "outval", 7 0; +E_0x55cf9dbdb160 .event anyedge, v0x55cf9dbcb910_0, v0x55cf9db86500_0; +S_0x55cf9dbdb5c0 .scope module, "Switch8_50" "TC_Switch" 4 65, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbdb7a0 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbdb7e0 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbdb820 .param/l "UUID" 0 16 2, C4<0010001101000101001110001011001001110011110000011010011010011111>; +v0x55cf9dbdbc00_0 .net "en", 0 0, v0x55cf9db86500_0; alias, 1 drivers +v0x55cf9dbdbcc0_0 .net "in", 7 0, L_0x55cf9dc34e70; alias, 1 drivers +v0x55cf9dbdbdb0_0 .net "out", 7 0, v0x55cf9dbdbe80_0; alias, 1 drivers +v0x55cf9dbdbe80_0 .var "outval", 7 0; +E_0x55cf9dbdbb80 .event anyedge, v0x55cf9db5cbc0_0, v0x55cf9db86500_0; +S_0x55cf9dbdbfe0 .scope module, "Switch8_51" "TC_Switch" 4 66, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbdc1c0 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbdc200 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbdc240 .param/l "UUID" 0 16 2, C4<0000011100000001001111111010010010101001001110101101101011001010>; +v0x55cf9dbdc490_0 .net "en", 0 0, v0x55cf9db89ee0_0; alias, 1 drivers +v0x55cf9dbdc550_0 .net "in", 7 0, L_0x55cf9dc47f80; alias, 1 drivers +v0x55cf9dbdc610_0 .net "out", 7 0, v0x55cf9dbdc710_0; alias, 1 drivers +v0x55cf9dbdc710_0 .var "outval", 7 0; +S_0x55cf9dbdc850 .scope module, "Switch8_52" "TC_Switch" 4 67, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbdca30 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbdca70 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbdcab0 .param/l "UUID" 0 16 2, C4<0001101110001101011101010001111111011111110101110111001101000011>; +v0x55cf9dbdcd00_0 .net "en", 0 0, v0x55cf9db87f80_0; alias, 1 drivers +v0x55cf9dbdcdc0_0 .net "in", 7 0, L_0x55cf9dc47ef0; alias, 1 drivers +v0x55cf9dbdce80_0 .net "out", 7 0, v0x55cf9dbdcf80_0; alias, 1 drivers +v0x55cf9dbdcf80_0 .var "outval", 7 0; +S_0x55cf9dbdd0c0 .scope module, "Switch8_53" "TC_Switch" 4 68, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbdd2a0 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbdd2e0 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbdd320 .param/l "UUID" 0 16 2, C4<0000111010111011000100111111011101010100000101010110101100001000>; +v0x55cf9dbdd680_0 .net "en", 0 0, v0x55cf9db87f80_0; alias, 1 drivers +v0x55cf9dbdd740_0 .net "in", 7 0, L_0x55cf9dc47f80; alias, 1 drivers +v0x55cf9dbdd800_0 .net "out", 7 0, v0x55cf9dbdd900_0; alias, 1 drivers +v0x55cf9dbdd900_0 .var "outval", 7 0; +S_0x55cf9dbdda40 .scope module, "Switch8_54" "TC_Switch" 4 69, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbddc20 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbddc60 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbddca0 .param/l "UUID" 0 16 2, C4<0011101111100101110100101010110011001110100110101010010111011010>; +v0x55cf9dbddf70_0 .net "en", 0 0, v0x55cf9db89ee0_0; alias, 1 drivers +v0x55cf9dbde030_0 .net "in", 7 0, L_0x55cf9dc47b80; alias, 1 drivers +v0x55cf9dbde120_0 .net "out", 7 0, v0x55cf9dbde1f0_0; alias, 1 drivers +v0x55cf9dbde1f0_0 .var "outval", 7 0; +E_0x55cf9dbddef0 .event anyedge, v0x55cf9db739d0_0, v0x55cf9db89ee0_0; +S_0x55cf9dbde350 .scope module, "Switch8_55" "TC_Switch" 4 70, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbde530 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbde570 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbde5b0 .param/l "UUID" 0 16 2, C4<0001101100010001110011010100011010100010110110010010110011111010>; +v0x55cf9dbde880_0 .net "en", 0 0, v0x55cf9db89ee0_0; alias, 1 drivers +v0x55cf9dbde940_0 .net "in", 7 0, L_0x55cf9dc47cd0; alias, 1 drivers +v0x55cf9dbdea30_0 .net "out", 7 0, v0x55cf9dbdeb00_0; alias, 1 drivers +v0x55cf9dbdeb00_0 .var "outval", 7 0; +E_0x55cf9dbde800 .event anyedge, v0x55cf9db4e6c0_0, v0x55cf9db89ee0_0; +S_0x55cf9dbdec60 .scope module, "Switch8_56" "TC_Switch" 4 71, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbdee40 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbdee80 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbdeec0 .param/l "UUID" 0 16 2, C4<0001110001010001100111011110101001111001000010011001111110001100>; +v0x55cf9dbdf190_0 .net "en", 0 0, v0x55cf9db87f80_0; alias, 1 drivers +v0x55cf9dbdf250_0 .net "in", 7 0, L_0x55cf9dc34b70; alias, 1 drivers +v0x55cf9dbdf340_0 .net "out", 7 0, v0x55cf9dbdf410_0; alias, 1 drivers +v0x55cf9dbdf410_0 .var "outval", 7 0; +E_0x55cf9dbdf110 .event anyedge, v0x55cf9db70620_0, v0x55cf9db87f80_0; +S_0x55cf9dbdf570 .scope module, "Switch8_57" "TC_Switch" 4 72, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbdf750 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbdf790 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbdf7d0 .param/l "UUID" 0 16 2, C4<0001101011100000101010010001100010011110110000000110011110111011>; +v0x55cf9dbdfaa0_0 .net "en", 0 0, v0x55cf9db87f80_0; alias, 1 drivers +v0x55cf9dbdfb60_0 .net "in", 7 0, L_0x55cf9dc34c10; alias, 1 drivers +v0x55cf9dbdfc50_0 .net "out", 7 0, v0x55cf9dbdfd20_0; alias, 1 drivers +v0x55cf9dbdfd20_0 .var "outval", 7 0; +E_0x55cf9dbdfa20 .event anyedge, v0x55cf9db6f910_0, v0x55cf9db87f80_0; +S_0x55cf9dbdfe80 .scope module, "Switch8_58" "TC_Switch" 4 73, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbe0060 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbe00a0 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbe00e0 .param/l "UUID" 0 16 2, C4<0000101000001010100101010001010001111100010000100110111000100100>; +v0x55cf9dbe0440_0 .net "en", 0 0, v0x55cf9db52ea0_0; alias, 1 drivers +v0x55cf9dbe0500_0 .net "in", 7 0, L_0x55cf9dc47ef0; alias, 1 drivers +v0x55cf9dbe05c0_0 .net "out", 7 0, v0x55cf9dbe06c0_0; alias, 1 drivers +v0x55cf9dbe06c0_0 .var "outval", 7 0; +S_0x55cf9dbe0820 .scope module, "Switch8_59" "TC_Switch" 4 74, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbe0a00 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbe0a40 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbe0a80 .param/l "UUID" 0 16 2, C4<0011010001000000111101110100000111010101110111010100100010000000>; +v0x55cf9dbe0cd0_0 .net "en", 0 0, v0x55cf9db52ea0_0; alias, 1 drivers +v0x55cf9dbe0d90_0 .net "in", 7 0, L_0x55cf9dc47f80; alias, 1 drivers +v0x55cf9dbe0e50_0 .net "out", 7 0, v0x55cf9dbe0f20_0; alias, 1 drivers +v0x55cf9dbe0f20_0 .var "outval", 7 0; +S_0x55cf9dbe1060 .scope module, "Switch8_60" "TC_Switch" 4 75, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbe1240 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbe1280 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbe12c0 .param/l "UUID" 0 16 2, C4<0000100001010001110001001010000011011110010000010101110011110100>; +v0x55cf9dbe1620_0 .net "en", 0 0, v0x55cf9db89ee0_0; alias, 1 drivers +v0x55cf9dbe16e0_0 .net "in", 7 0, L_0x55cf9dc47ef0; alias, 1 drivers +v0x55cf9dbe17a0_0 .net "out", 7 0, v0x55cf9dbe18a0_0; alias, 1 drivers +v0x55cf9dbe18a0_0 .var "outval", 7 0; +S_0x55cf9dbe19e0 .scope module, "Switch8_61" "TC_Switch" 4 76, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbe1fd0 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbe2010 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbe2050 .param/l "UUID" 0 16 2, C4<0010101100110010100001010101011000010101001000101000110111000011>; +v0x55cf9dbe23b0_0 .net "en", 0 0, v0x55cf9db89ee0_0; alias, 1 drivers +v0x55cf9dbe2470_0 .net "in", 7 0, L_0x55cf9dc47f80; alias, 1 drivers +v0x55cf9dbe2530_0 .net "out", 7 0, v0x55cf9dbe2630_0; alias, 1 drivers +v0x55cf9dbe2630_0 .var "outval", 7 0; +S_0x55cf9dbe2770 .scope module, "Switch8_62" "TC_Switch" 4 77, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbe2950 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbe2990 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbe29d0 .param/l "UUID" 0 16 2, C4<0011100011100100001110011010000100011101101100010100010000101011>; +v0x55cf9dbe2c20_0 .net "en", 0 0, v0x55cf9db87f80_0; alias, 1 drivers +v0x55cf9dbe2ce0_0 .net "in", 7 0, L_0x55cf9dc47f80; alias, 1 drivers +v0x55cf9dbe2da0_0 .net "out", 7 0, v0x55cf9dbe2ea0_0; alias, 1 drivers +v0x55cf9dbe2ea0_0 .var "outval", 7 0; +S_0x55cf9dbe2fe0 .scope module, "Switch8_63" "TC_Switch" 4 78, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbe31c0 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbe3200 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbe3240 .param/l "UUID" 0 16 2, C4<0000111010101111101010100011101100110001001001011111010111101001>; +v0x55cf9dbe3490_0 .net "en", 0 0, v0x55cf9db87240_0; alias, 1 drivers +v0x55cf9dbe3550_0 .net "in", 7 0, L_0x55cf9dc47ef0; alias, 1 drivers +v0x55cf9dbe3610_0 .net "out", 7 0, v0x55cf9dbe3710_0; alias, 1 drivers +v0x55cf9dbe3710_0 .var "outval", 7 0; +S_0x55cf9dbe3870 .scope module, "Switch8_64" "TC_Switch" 4 79, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbe3a50 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbe3a90 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbe3ad0 .param/l "UUID" 0 16 2, C4<0001000101110111000111111000011101111010001101001100001010000101>; +v0x55cf9dbe3d20_0 .net "en", 0 0, v0x55cf9db87240_0; alias, 1 drivers +v0x55cf9dbe3de0_0 .net "in", 7 0, L_0x55cf9dc47f80; alias, 1 drivers +v0x55cf9dbe3ea0_0 .net "out", 7 0, v0x55cf9dbe3f70_0; alias, 1 drivers +v0x55cf9dbe3f70_0 .var "outval", 7 0; +S_0x55cf9dbe40b0 .scope module, "Switch8_65" "TC_Switch" 4 80, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbe4290 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbe42d0 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbe4310 .param/l "UUID" 0 16 2, C4<0010011011000001101001101110100010101101001000000110101010001111>; +v0x55cf9dbe4560_0 .net "en", 0 0, v0x55cf9db87f80_0; alias, 1 drivers +v0x55cf9dbe4620_0 .net "in", 7 0, L_0x55cf9dc47ef0; alias, 1 drivers +v0x55cf9dbe46e0_0 .net "out", 7 0, v0x55cf9dbe47e0_0; alias, 1 drivers +v0x55cf9dbe47e0_0 .var "outval", 7 0; +S_0x55cf9dbe4920 .scope module, "Switch8_66" "TC_Switch" 4 81, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbe4b00 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbe4b40 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbe4b80 .param/l "UUID" 0 16 2, C4<0001100111110011010111101000100000010100001101111101010001100110>; +v0x55cf9dbe4e50_0 .net "en", 0 0, v0x55cf9db89ee0_0; alias, 1 drivers +v0x55cf9dbe4f10_0 .net "in", 7 0, L_0x55cf9dc455a0; alias, 1 drivers +v0x55cf9dbe5000_0 .net "out", 7 0, v0x55cf9dbe50d0_0; alias, 1 drivers +v0x55cf9dbe50d0_0 .var "outval", 7 0; +E_0x55cf9dbe4dd0 .event anyedge, v0x55cf9db4f680_0, v0x55cf9db89ee0_0; +S_0x55cf9dbe5230 .scope module, "Switch8_67" "TC_Switch" 4 82, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbe5410 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbe5450 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbe5490 .param/l "UUID" 0 16 2, C4<0001000010100000111010000011000101111101000010111001101010000100>; +v0x55cf9dbe5760_0 .net "en", 0 0, v0x55cf9db52ea0_0; alias, 1 drivers +v0x55cf9dbe5820_0 .net "in", 7 0, L_0x55cf9dc34f10; alias, 1 drivers +v0x55cf9dbe5910_0 .net "out", 7 0, v0x55cf9dbe59e0_0; alias, 1 drivers +v0x55cf9dbe59e0_0 .var "outval", 7 0; +E_0x55cf9dbe56e0 .event anyedge, v0x55cf9dbc95c0_0, v0x55cf9db52ea0_0; +S_0x55cf9dbe5b40 .scope module, "Switch8_68" "TC_Switch" 4 83, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbe5d20 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbe5d60 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbe5da0 .param/l "UUID" 0 16 2, C4<0010000111101010101100111100011000001010010101110010101100110010>; +v0x55cf9dbe6070_0 .net "en", 0 0, v0x55cf9db87f80_0; alias, 1 drivers +v0x55cf9dbe6130_0 .net "in", 7 0, L_0x55cf9dc457e0; alias, 1 drivers +v0x55cf9dbe6220_0 .net "out", 7 0, v0x55cf9dbe62f0_0; alias, 1 drivers +v0x55cf9dbe62f0_0 .var "outval", 7 0; +E_0x55cf9dbe5ff0 .event anyedge, v0x55cf9da76480_0, v0x55cf9db87f80_0; +S_0x55cf9dbe6450 .scope module, "Switch8_69" "TC_Switch" 4 84, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbe6630 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbe6670 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbe66b0 .param/l "UUID" 0 16 2, C4<0010000101010000001011010101101110011011110100101110101101001010>; +v0x55cf9dbe6980_0 .net "en", 0 0, v0x55cf9db87240_0; alias, 1 drivers +v0x55cf9dbe6a40_0 .net "in", 7 0, L_0x55cf9dc45880; alias, 1 drivers +v0x55cf9dbe6b30_0 .net "out", 7 0, v0x55cf9dbe6c00_0; alias, 1 drivers +v0x55cf9dbe6c00_0 .var "outval", 7 0; +E_0x55cf9dbe6900 .event anyedge, v0x55cf9dbb7c90_0, v0x55cf9db87240_0; +S_0x55cf9dbe6d60 .scope module, "Switch8_73" "TC_Switch" 4 88, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbe6f40 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbe6f80 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbe6fc0 .param/l "UUID" 0 16 2, C4<0011110100101101011101110000111001110000110001010111001111100100>; +v0x55cf9dbe73a0_0 .net "en", 0 0, v0x55cf9db7c8f0_0; alias, 1 drivers +v0x55cf9dbe7490_0 .net "in", 7 0, L_0x55cf9dc48330; alias, 1 drivers +v0x55cf9dbe7550_0 .net "out", 7 0, v0x55cf9dbe7640_0; alias, 1 drivers +v0x55cf9dbe7640_0 .var "outval", 7 0; +E_0x55cf9dbe7320 .event anyedge, v0x55cf9dbe7490_0, v0x55cf9db7c8f0_0; +S_0x55cf9dbe77a0 .scope module, "Switch8_74" "TC_Switch" 4 89, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbe7980 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbe79c0 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbe7a00 .param/l "UUID" 0 16 2, C4<0000010001101100110100111010010000111001101000000110010001000000>; +v0x55cf9dbe7cd0_0 .net "en", 0 0, v0x55cf9db7bc10_0; alias, 1 drivers +v0x55cf9dbe7de0_0 .net "in", 7 0, L_0x55cf9dc48bf0; alias, 1 drivers +v0x55cf9dbe7ec0_0 .net "out", 7 0, v0x55cf9dbe7f80_0; alias, 1 drivers +v0x55cf9dbe7f80_0 .var "outval", 7 0; +E_0x55cf9dbe7c50 .event anyedge, v0x55cf9dbe7de0_0, v0x55cf9db98350_0; +S_0x55cf9dbe80e0 .scope module, "Switch8_75" "TC_Switch" 4 90, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbe82c0 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbe8300 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbe8340 .param/l "UUID" 0 16 2, C4<0010101011100011011101110101001000001010001110001011111100101010>; +v0x55cf9dbe8610_0 .net "en", 0 0, v0x55cf9db7af30_0; alias, 1 drivers +v0x55cf9dbe8700_0 .net "in", 7 0, L_0x55cf9dc48830; alias, 1 drivers +v0x55cf9dbe87c0_0 .net "out", 7 0, v0x55cf9dbe88b0_0; alias, 1 drivers +v0x55cf9dbe88b0_0 .var "outval", 7 0; +E_0x55cf9dbe8590 .event anyedge, v0x55cf9dbe8700_0, v0x55cf9db7af30_0; +S_0x55cf9dbe8a10 .scope module, "Switch8_79" "TC_Switch" 4 94, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbe8bf0 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbe8c30 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbe8c70 .param/l "UUID" 0 16 2, C4<0011001000001001100010010000010010100001110110001011101001110010>; +L_0x55cf9dc47e00 .functor BUFZ 8, v0x55cf9dbe9130_0, C4<00000000>, C4<00000000>, C4<00000000>; +v0x55cf9dbe8ec0_0 .net "en", 0 0, v0x55cf9db89ee0_0; alias, 1 drivers +v0x55cf9dbe8f80_0 .net "in", 7 0, L_0x55cf9dc47ef0; alias, 1 drivers +v0x55cf9dbe9040_0 .net "out", 7 0, L_0x55cf9dc47e00; 1 drivers +v0x55cf9dbe9130_0 .var "outval", 7 0; +S_0x55cf9dbe9290 .scope module, "Switch8_8" "TC_Switch" 4 23, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbe9470 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbe94b0 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbe94f0 .param/l "UUID" 0 16 2, C4<0000110011000100000000110101011100001101100100000010101010011010>; +v0x55cf9dbe9740_0 .net "en", 0 0, v0x55cf9db87240_0; alias, 1 drivers +v0x55cf9dbe9800_0 .net "in", 7 0, L_0x55cf9dc47f80; alias, 1 drivers +v0x55cf9dbe98c0_0 .net "out", 7 0, v0x55cf9dbe99c0_0; alias, 1 drivers +v0x55cf9dbe99c0_0 .var "outval", 7 0; +S_0x55cf9dbe9b00 .scope module, "Switch8_9" "TC_Switch" 4 24, 16 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbe9ce0 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbe9d20 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dbe9d60 .param/l "UUID" 0 16 2, C4<0010001101100101010101001111011000011001110001001001000011111111>; +v0x55cf9dbe9fb0_0 .net "en", 0 0, v0x55cf9db87240_0; alias, 1 drivers +v0x55cf9dbea070_0 .net "in", 7 0, L_0x55cf9dc47ef0; alias, 1 drivers +v0x55cf9dbea130_0 .net "out", 7 0, v0x55cf9dbea230_0; alias, 1 drivers +v0x55cf9dbea230_0 .var "outval", 7 0; +S_0x55cf9dbea370 .scope module, "Xnor8_28" "TC_Xnor" 4 43, 22 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in0"; + .port_info 1 /INPUT 8 "in1"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbea550 .param/l "BIT_WIDTH" 0 22 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbea590 .param/str "NAME" 0 22 3, "\000"; +P_0x55cf9dbea5d0 .param/l "UUID" 0 22 2, C4<0001010010111001010011000001111000000001110001000001111011110111>; +L_0x55cf9dc34a20 .functor XNOR 8, v0x55cf9dbd6d60_0, v0x55cf9dbd6530_0, C4<00000000>, C4<00000000>; +v0x55cf9dbea820_0 .net "in0", 7 0, v0x55cf9dbd6d60_0; alias, 1 drivers +v0x55cf9dbea930_0 .net "in1", 7 0, v0x55cf9dbd6530_0; alias, 1 drivers +v0x55cf9dbeaa00_0 .net "out", 7 0, L_0x55cf9dc34a20; alias, 1 drivers +S_0x55cf9dbeab40 .scope module, "Xor8_29" "TC_Xor" 4 44, 23 1 0, S_0x55cf9dbb4260; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in0"; + .port_info 1 /INPUT 8 "in1"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dbead20 .param/l "BIT_WIDTH" 0 23 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbead60 .param/str "NAME" 0 23 3, "\000"; +P_0x55cf9dbeada0 .param/l "UUID" 0 23 2, C4<0001000101010110100100001001011100001011101001001100001100000100>; +L_0x55cf9dc34a90 .functor XOR 8, v0x55cf9dbd4a10_0, v0x55cf9dbd4060_0, C4<00000000>, C4<00000000>; +v0x55cf9dbeaff0_0 .net "in0", 7 0, v0x55cf9dbd4a10_0; alias, 1 drivers +v0x55cf9dbeb100_0 .net "in1", 7 0, v0x55cf9dbd4060_0; alias, 1 drivers +v0x55cf9dbeb1d0_0 .net "out", 7 0, L_0x55cf9dc34a90; alias, 1 drivers +S_0x55cf9dbf3740 .scope module, "And_32" "TC_And" 3 44, 6 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "in0"; + .port_info 1 /INPUT 1 "in1"; + .port_info 2 /OUTPUT 1 "out"; +P_0x55cf9dbf3920 .param/l "BIT_WIDTH" 0 6 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dbf3960 .param/str "NAME" 0 6 3, "\000"; +P_0x55cf9dbf39a0 .param/l "UUID" 0 6 2, C4<0010100110110101011100101111010111011100000001100000111001000100>; +L_0x55cf9dc4ad70 .functor AND 1, L_0x55cf9dc4e250, L_0x55cf9dc50920, C4<1>, C4<1>; +v0x55cf9dbf3bd0_0 .net "in0", 0 0, L_0x55cf9dc4e250; alias, 1 drivers +v0x55cf9dbf3c70_0 .net "in1", 0 0, L_0x55cf9dc50920; alias, 1 drivers +v0x55cf9dbf3d10_0 .net "out", 0 0, L_0x55cf9dc4ad70; alias, 1 drivers +S_0x55cf9dbf3db0 .scope module, "And_43" "TC_And" 3 55, 6 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "in0"; + .port_info 1 /INPUT 1 "in1"; + .port_info 2 /OUTPUT 1 "out"; +P_0x55cf9dbf3f90 .param/l "BIT_WIDTH" 0 6 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dbf3fd0 .param/str "NAME" 0 6 3, "\000"; +P_0x55cf9dbf4010 .param/l "UUID" 0 6 2, C4<0010010110100001100011010001100100001101110101101110001111110110>; +L_0x55cf9dc4b860 .functor AND 1, L_0x55cf9dc4e6b0, L_0x55cf9dc4b7d0, C4<1>, C4<1>; +v0x55cf9dbf4240_0 .net "in0", 0 0, L_0x55cf9dc4e6b0; alias, 1 drivers +v0x55cf9dbf42e0_0 .net "in1", 0 0, L_0x55cf9dc4b7d0; alias, 1 drivers +v0x55cf9dbf4380_0 .net "out", 0 0, L_0x55cf9dc4b860; alias, 1 drivers +S_0x55cf9dbf44e0 .scope module, "Buffer1_24" "TC_Buffer" 3 36, 24 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "in"; + .port_info 1 /OUTPUT 1 "out"; +P_0x55cf9dbf46c0 .param/l "BIT_WIDTH" 0 24 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dbf4700 .param/str "NAME" 0 24 3, "\000"; +P_0x55cf9dbf4740 .param/l "UUID" 0 24 2, C4<0010111001110101100000111001101101011000110110110000110101111011>; +L_0x55cf9dc4a530 .functor BUFZ 1, L_0x55cf9dc4e430, C4<0>, C4<0>, C4<0>; +v0x55cf9dbf4960_0 .net "in", 0 0, L_0x55cf9dc4e430; alias, 1 drivers +v0x55cf9dbf4a60_0 .net "out", 0 0, L_0x55cf9dc4a530; alias, 1 drivers +S_0x55cf9dbf4ba0 .scope module, "Buffer1_35" "TC_Buffer" 3 47, 24 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "in"; + .port_info 1 /OUTPUT 1 "out"; +P_0x55cf9dbf4dd0 .param/l "BIT_WIDTH" 0 24 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dbf4e10 .param/str "NAME" 0 24 3, "\000"; +P_0x55cf9dbf4e50 .param/l "UUID" 0 24 2, C4<0001111100000101101001000011100100000011011000000011000111011010>; +L_0x55cf9dc4afc0 .functor BUFZ 1, L_0x55cf9dc4aa00, C4<0>, C4<0>, C4<0>; +v0x55cf9dbf5050_0 .net "in", 0 0, L_0x55cf9dc4aa00; alias, 1 drivers +v0x55cf9dbf5150_0 .net "out", 0 0, L_0x55cf9dc4afc0; alias, 1 drivers +S_0x55cf9dbf5290 .scope module, "Buffer1_37" "TC_Buffer" 3 49, 24 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "in"; + .port_info 1 /OUTPUT 1 "out"; +P_0x55cf9dbf5470 .param/l "BIT_WIDTH" 0 24 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dbf54b0 .param/str "NAME" 0 24 3, "\000"; +P_0x55cf9dbf54f0 .param/l "UUID" 0 24 2, C4<0001111110111010101000001000000111010101101101001110100101101111>; +L_0x55cf9dc4b220 .functor BUFZ 1, L_0x55cf9dc49160, C4<0>, C4<0>, C4<0>; +v0x55cf9dbf5730_0 .net "in", 0 0, L_0x55cf9dc49160; alias, 1 drivers +v0x55cf9dbf5810_0 .net "out", 0 0, L_0x55cf9dc4b220; alias, 1 drivers +S_0x55cf9dbf5930 .scope module, "Buffer1_40" "TC_Buffer" 3 52, 24 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "in"; + .port_info 1 /OUTPUT 1 "out"; +P_0x55cf9dbf5b10 .param/l "BIT_WIDTH" 0 24 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dbf5b50 .param/str "NAME" 0 24 3, "\000"; +P_0x55cf9dbf5b90 .param/l "UUID" 0 24 2, C4<0010011001111111101010110001000111000001110011000100111011000110>; +L_0x55cf9dc4b5e0 .functor BUFZ 1, v0x55cf9dc0acc0_0, C4<0>, C4<0>, C4<0>; +v0x55cf9dbf5dd0_0 .net "in", 0 0, v0x55cf9dc0acc0_0; alias, 1 drivers +v0x55cf9dbf5ed0_0 .net "out", 0 0, L_0x55cf9dc4b5e0; alias, 1 drivers +S_0x55cf9dbf6010 .scope module, "Buffer1_41" "TC_Buffer" 3 53, 24 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "in"; + .port_info 1 /OUTPUT 1 "out"; +P_0x55cf9dbf61f0 .param/l "BIT_WIDTH" 0 24 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dbf6230 .param/str "NAME" 0 24 3, "\000"; +P_0x55cf9dbf6270 .param/l "UUID" 0 24 2, C4<0001111101011011001000001001001111100100001100011000000010000000>; +L_0x55cf9dc4b690 .functor BUFZ 1, v0x55cf9dc09c90_0, C4<0>, C4<0>, C4<0>; +v0x55cf9dbf64b0_0 .net "in", 0 0, v0x55cf9dc09c90_0; alias, 1 drivers +v0x55cf9dbf65b0_0 .net "out", 0 0, L_0x55cf9dc4b690; alias, 1 drivers +S_0x55cf9dbf66f0 .scope module, "Buffer8_10" "TC_Buffer" 3 22, 24 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /OUTPUT 8 "out"; +P_0x55cf9dbf68d0 .param/l "BIT_WIDTH" 0 24 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbf6910 .param/str "NAME" 0 24 3, "\000"; +P_0x55cf9dbf6950 .param/l "UUID" 0 24 2, C4<0010110011100010100111111100011000010100111111011101000101010001>; +L_0x55cf9dc49580 .functor BUFZ 8, L_0x55cf9dc4cb40, C4<00000000>, C4<00000000>, C4<00000000>; +v0x55cf9dbf6b40_0 .net "in", 7 0, L_0x55cf9dc4cb40; alias, 1 drivers +v0x55cf9dbf6c40_0 .net "out", 7 0, L_0x55cf9dc49580; alias, 1 drivers +S_0x55cf9dbf6d80 .scope module, "Buffer8_11" "TC_Buffer" 3 23, 24 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /OUTPUT 8 "out"; +P_0x55cf9dbf6f60 .param/l "BIT_WIDTH" 0 24 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbf6fa0 .param/str "NAME" 0 24 3, "\000"; +P_0x55cf9dbf6fe0 .param/l "UUID" 0 24 2, C4<0001110101100100111100010001000010010111101001100010011100001100>; +L_0x55cf9dc49680 .functor BUFZ 8, L_0x55cf9dc4ce40, C4<00000000>, C4<00000000>, C4<00000000>; +v0x55cf9dbf7220_0 .net "in", 7 0, L_0x55cf9dc4ce40; alias, 1 drivers +v0x55cf9dbf7320_0 .net "out", 7 0, L_0x55cf9dc49680; alias, 1 drivers +S_0x55cf9dbf7460 .scope module, "Buffer8_12" "TC_Buffer" 3 24, 24 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /OUTPUT 8 "out"; +P_0x55cf9dbf7640 .param/l "BIT_WIDTH" 0 24 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbf7680 .param/str "NAME" 0 24 3, "\000"; +P_0x55cf9dbf76c0 .param/l "UUID" 0 24 2, C4<0010110100010001111001000111011110100011111110110011011011101100>; +L_0x55cf9dc497a0 .functor BUFZ 8, L_0x55cf9dc4d140, C4<00000000>, C4<00000000>, C4<00000000>; +v0x55cf9dbf7900_0 .net "in", 7 0, L_0x55cf9dc4d140; alias, 1 drivers +v0x55cf9dbf7a00_0 .net "out", 7 0, L_0x55cf9dc497a0; alias, 1 drivers +S_0x55cf9dbf7b40 .scope module, "Buffer8_13" "TC_Buffer" 3 25, 24 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /OUTPUT 8 "out"; +P_0x55cf9dbf7d20 .param/l "BIT_WIDTH" 0 24 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbf7d60 .param/str "NAME" 0 24 3, "\000"; +P_0x55cf9dbf7da0 .param/l "UUID" 0 24 2, C4<0011010010000010001101010111011010011111010100010001100000111001>; +L_0x55cf9dc498e0 .functor BUFZ 8, L_0x55cf9dc4d4b0, C4<00000000>, C4<00000000>, C4<00000000>; +v0x55cf9dbf7fe0_0 .net "in", 7 0, L_0x55cf9dc4d4b0; alias, 1 drivers +v0x55cf9dbf80e0_0 .net "out", 7 0, L_0x55cf9dc498e0; alias, 1 drivers +S_0x55cf9dbf8220 .scope module, "Buffer8_14" "TC_Buffer" 3 26, 24 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /OUTPUT 8 "out"; +P_0x55cf9dbf8400 .param/l "BIT_WIDTH" 0 24 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbf8440 .param/str "NAME" 0 24 3, "\000"; +P_0x55cf9dbf8480 .param/l "UUID" 0 24 2, C4<0000000101101000100100111011011100111000110100110110111101100111>; +L_0x55cf9dc49990 .functor BUFZ 8, L_0x55cf9dc4d8b0, C4<00000000>, C4<00000000>, C4<00000000>; +v0x55cf9dbf86c0_0 .net "in", 7 0, L_0x55cf9dc4d8b0; alias, 1 drivers +v0x55cf9dbf87c0_0 .net "out", 7 0, L_0x55cf9dc49990; alias, 1 drivers +S_0x55cf9dbf8900 .scope module, "Buffer8_15" "TC_Buffer" 3 27, 24 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /OUTPUT 8 "out"; +P_0x55cf9dbf8ae0 .param/l "BIT_WIDTH" 0 24 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbf8b20 .param/str "NAME" 0 24 3, "\000"; +P_0x55cf9dbf8b60 .param/l "UUID" 0 24 2, C4<0001011011011111110010100000101001101101000010010100101101110011>; +L_0x55cf9dc49a90 .functor BUFZ 8, v0x55cf9dc27700_0, C4<00000000>, C4<00000000>, C4<00000000>; +v0x55cf9dbf8da0_0 .net "in", 7 0, v0x55cf9dc27700_0; alias, 1 drivers +v0x55cf9dbf8ea0_0 .net "out", 7 0, L_0x55cf9dc49a90; alias, 1 drivers +S_0x55cf9dbf8fe0 .scope module, "Buffer8_16" "TC_Buffer" 3 28, 24 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /OUTPUT 8 "out"; +P_0x55cf9dbf91c0 .param/l "BIT_WIDTH" 0 24 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbf9200 .param/str "NAME" 0 24 3, "\000"; +P_0x55cf9dbf9240 .param/l "UUID" 0 24 2, C4<0000010000011111110110101000111100101011001010101001001101010001>; +L_0x55cf9dc49b40 .functor BUFZ 8, v0x55cf9dc0c230_0, C4<00000000>, C4<00000000>, C4<00000000>; +v0x55cf9dbf9480_0 .net "in", 7 0, v0x55cf9dc0c230_0; alias, 1 drivers +v0x55cf9dbf9580_0 .net "out", 7 0, L_0x55cf9dc49b40; alias, 1 drivers +S_0x55cf9dbf96c0 .scope module, "Buffer8_36" "TC_Buffer" 3 48, 24 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /OUTPUT 8 "out"; +P_0x55cf9dbf98a0 .param/l "BIT_WIDTH" 0 24 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbf98e0 .param/str "NAME" 0 24 3, "\000"; +P_0x55cf9dbf9920 .param/l "UUID" 0 24 2, C4<0001110000110101001110010100101100011000011110001011000110100010>; +L_0x55cf9dc4b100 .functor BUFZ 8, v0x55cf9dc06760_0, C4<00000000>, C4<00000000>, C4<00000000>; +v0x55cf9dbf9b60_0 .net "in", 7 0, v0x55cf9dc06760_0; alias, 1 drivers +v0x55cf9dbf9c60_0 .net "out", 7 0, L_0x55cf9dc4b100; 1 drivers +S_0x55cf9dbf9da0 .scope module, "Buffer8_45" "TC_Buffer" 3 57, 24 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /OUTPUT 8 "out"; +P_0x55cf9dbf9f80 .param/l "BIT_WIDTH" 0 24 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbf9fc0 .param/str "NAME" 0 24 3, "\000"; +P_0x55cf9dbfa000 .param/l "UUID" 0 24 2, C4<0001001000100010101100000001101011111000101100101110010010010011>; +L_0x55cf9dc4bb90 .functor BUFZ 8, L_0x55cf9dc4ba40, C4<00000000>, C4<00000000>, C4<00000000>; +v0x55cf9dbfa240_0 .net "in", 7 0, L_0x55cf9dc4ba40; alias, 1 drivers +v0x55cf9dbfa340_0 .net "out", 7 0, L_0x55cf9dc4bb90; alias, 1 drivers +S_0x55cf9dbfa440 .scope module, "Buffer8_46" "TC_Buffer" 3 58, 24 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /OUTPUT 8 "out"; +P_0x55cf9dbfa620 .param/l "BIT_WIDTH" 0 24 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbfa660 .param/str "NAME" 0 24 3, "\000"; +P_0x55cf9dbfa6a0 .param/l "UUID" 0 24 2, C4<0011111111011000101011011110111101101000101101010111011100100011>; +L_0x55cf9dc4bd60 .functor BUFZ 8, L_0x55cf9dc4b9a0, C4<00000000>, C4<00000000>, C4<00000000>; +v0x55cf9dbfa8e0_0 .net "in", 7 0, L_0x55cf9dc4b9a0; alias, 1 drivers +v0x55cf9dbfa9e0_0 .net "out", 7 0, L_0x55cf9dc4bd60; alias, 1 drivers +S_0x55cf9dbfaae0 .scope module, "Buffer8_48" "TC_Buffer" 3 60, 24 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /OUTPUT 8 "out"; +P_0x55cf9dbfacc0 .param/l "BIT_WIDTH" 0 24 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbfad00 .param/str "NAME" 0 24 3, "\000"; +P_0x55cf9dbfad40 .param/l "UUID" 0 24 2, C4<0001100011100111001011001110110011011100000101010101000000001100>; +L_0x55cf9dc4c050 .functor BUFZ 8, L_0x55cf9dc48fe0, C4<00000000>, C4<00000000>, C4<00000000>; +v0x55cf9dbfaf80_0 .net "in", 7 0, L_0x55cf9dc48fe0; alias, 1 drivers +v0x55cf9dbfb060_0 .net "out", 7 0, L_0x55cf9dc4c050; alias, 1 drivers +S_0x55cf9dbfb180 .scope module, "Buffer8_49" "TC_Buffer" 3 61, 24 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /OUTPUT 8 "out"; +P_0x55cf9dbfb360 .param/l "BIT_WIDTH" 0 24 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbfb3a0 .param/str "NAME" 0 24 3, "\000"; +P_0x55cf9dbfb3e0 .param/l "UUID" 0 24 2, C4<0011010001011001110010010010110101100001101101110000100000001101>; +L_0x55cf9dc4c190 .functor BUFZ 8, v0x55cf9db59750_0, C4<00000000>, C4<00000000>, C4<00000000>; +v0x55cf9dbfb620_0 .net "in", 7 0, v0x55cf9db59750_0; alias, 1 drivers +v0x55cf9dbfb750_0 .net "out", 7 0, L_0x55cf9dc4c190; alias, 1 drivers +S_0x55cf9dbfb890 .scope module, "Buffer8_8" "TC_Buffer" 3 20, 24 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /OUTPUT 8 "out"; +P_0x55cf9dbfba70 .param/l "BIT_WIDTH" 0 24 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbfbab0 .param/str "NAME" 0 24 3, "\000"; +P_0x55cf9dbfbaf0 .param/l "UUID" 0 24 2, C4<0011001000000000001010001101110001101101100100010011110001011110>; +L_0x55cf9dc49410 .functor BUFZ 8, v0x55cf9dc11140_0, C4<00000000>, C4<00000000>, C4<00000000>; +v0x55cf9dbfbd30_0 .net "in", 7 0, v0x55cf9dc11140_0; alias, 1 drivers +v0x55cf9dbfbe30_0 .net "out", 7 0, L_0x55cf9dc49410; alias, 1 drivers +S_0x55cf9dbfbf70 .scope module, "Buffer8_9" "TC_Buffer" 3 21, 24 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /OUTPUT 8 "out"; +P_0x55cf9dbfc150 .param/l "BIT_WIDTH" 0 24 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dbfc190 .param/str "NAME" 0 24 3, "\000"; +P_0x55cf9dbfc1d0 .param/l "UUID" 0 24 2, C4<0000111001100010000010101001001101101000100011100101101101011011>; +L_0x55cf9dc49480 .functor BUFZ 8, L_0x55cf9dc4c6a0, C4<00000000>, C4<00000000>, C4<00000000>; +v0x55cf9dbfc410_0 .net "in", 7 0, L_0x55cf9dc4c6a0; alias, 1 drivers +v0x55cf9dbfc510_0 .net "out", 7 0, L_0x55cf9dc49480; alias, 1 drivers +S_0x55cf9dbfc650 .scope module, "COND_58" "COND" 3 70, 25 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 8 "Condition"; + .port_info 3 /INPUT 8 "Input"; + .port_info 4 /OUTPUT 1 "Result"; +P_0x55cf9db865c0 .param/str "NAME" 0 25 3, "\000"; +P_0x55cf9db86600 .param/l "UUID" 0 25 2, C4<0001101110010010010100000100010110001110111001000011100100010110>; +L_0x55cf9dc50920 .functor BUFZ 1, L_0x55cf9dc50750, C4<0>, C4<0>, C4<0>; +L_0x55cf9dc50a60 .functor BUFZ 8, v0x55cf9dc29c80_0, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x55cf9dc50b80 .functor BUFZ 8, L_0x55cf9dc4d140, C4<00000000>, C4<00000000>, C4<00000000>; +v0x55cf9dc04230_0 .net "Condition", 7 0, v0x55cf9dc29c80_0; alias, 1 drivers +v0x55cf9dc04310_0 .net "Input", 7 0, L_0x55cf9dc4d140; alias, 1 drivers +v0x55cf9dc04400_0 .net "Result", 0 0, L_0x55cf9dc50920; alias, 1 drivers +v0x55cf9dc04500_0 .net "clk", 0 0, v0x55cf9dc31950_0; alias, 1 drivers +v0x55cf9dc045a0_0 .net "rst", 0 0, v0x55cf9dc32230_0; alias, 1 drivers +v0x55cf9dc04690_0 .net "wire_0", 0 0, L_0x55cf9dc4ee80; 1 drivers +v0x55cf9dc04730_0 .net "wire_1", 0 0, L_0x55cf9dc4ea90; 1 drivers +v0x55cf9dc04820_0 .net "wire_10", 0 0, L_0x55cf9dc50190; 1 drivers +v0x55cf9dc04910_0 .net "wire_11", 0 0, L_0x55cf9dc4ef20; 1 drivers +v0x55cf9dc04a60_0 .net "wire_12", 0 0, L_0x55cf9dc50750; 1 drivers +v0x55cf9dc04b20_0 .net "wire_13", 0 0, L_0x55cf9dc4f310; 1 drivers +v0x55cf9dc04c10_0 .net "wire_14", 7 0, L_0x55cf9dc50a60; 1 drivers +v0x55cf9dc04cd0_0 .net "wire_15", 0 0, L_0x55cf9dc4f060; 1 drivers +v0x55cf9dc04dc0_0 .net "wire_16", 0 0, L_0x55cf9dc503d0; 1 drivers +v0x55cf9dc04ed0_0 .net "wire_17", 7 0, L_0x55cf9dc50b80; 1 drivers +v0x55cf9dc04f90_0 .net "wire_18", 0 0, L_0x55cf9dc4f230; 1 drivers +v0x55cf9dc05080_0 .net "wire_19", 0 0, L_0x55cf9dc4f720; 1 drivers +v0x55cf9dc05190_0 .net "wire_2", 0 0, v0x55cf9dc03930_0; 1 drivers +v0x55cf9dc052a0_0 .net "wire_20", 0 0, L_0x55cf9dc4fb60; 1 drivers +v0x55cf9dc053b0_0 .net "wire_21", 0 0, L_0x55cf9dc4fd10; 1 drivers +v0x55cf9dc054c0_0 .net "wire_22", 0 0, v0x55cf9dc03000_0; 1 drivers +v0x55cf9dc055d0_0 .net "wire_23", 0 0, L_0x55cf9dc4f920; 1 drivers +v0x55cf9dc056e0_0 .net "wire_3", 0 0, L_0x55cf9dc4f190; 1 drivers +v0x55cf9dc057f0_0 .net "wire_4", 0 0, L_0x55cf9dc4f3b0; 1 drivers +v0x55cf9dc05900_0 .net "wire_5", 0 0, L_0x55cf9dc4ec10; 1 drivers +v0x55cf9dc05a10_0 .net "wire_6", 0 0, L_0x55cf9dc4ff50; 1 drivers +v0x55cf9dc05b20_0 .net "wire_7", 0 0, L_0x55cf9dc50580; 1 drivers +v0x55cf9dc05c30_0 .net "wire_8", 0 0, L_0x55cf9dc4eb70; 1 drivers +v0x55cf9dc05d40_0 .net "wire_9", 0 0, L_0x55cf9dc4efc0; 1 drivers +S_0x55cf9dbfc920 .scope module, "Nand_6" "TC_Nand" 25 17, 11 1 0, S_0x55cf9dbfc650; + .timescale -8 -9; + .port_info 0 /INPUT 1 "in0"; + .port_info 1 /INPUT 1 "in1"; + .port_info 2 /OUTPUT 1 "out"; +P_0x55cf9dbfcb20 .param/l "BIT_WIDTH" 0 11 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dbfcb60 .param/str "NAME" 0 11 3, "\000"; +P_0x55cf9dbfcba0 .param/l "UUID" 0 11 2, C4<0000101101011110101000111010111101101010010000011110010100110001>; +L_0x55cf9dc4fda0 .functor AND 1, L_0x55cf9dc4f720, L_0x55cf9dc4f920, C4<1>, C4<1>; +L_0x55cf9dc4ff50 .functor NOT 1, L_0x55cf9dc4fda0, C4<0>, C4<0>, C4<0>; +v0x55cf9dbfce10_0 .net *"_ivl_0", 0 0, L_0x55cf9dc4fda0; 1 drivers +v0x55cf9dbfcf10_0 .net "in0", 0 0, L_0x55cf9dc4f720; alias, 1 drivers +v0x55cf9dbfcff0_0 .net "in1", 0 0, L_0x55cf9dc4f920; alias, 1 drivers +v0x55cf9dbfd0b0_0 .net "out", 0 0, L_0x55cf9dc4ff50; alias, 1 drivers +S_0x55cf9dbfd210 .scope module, "Nand_7" "TC_Nand" 25 18, 11 1 0, S_0x55cf9dbfc650; + .timescale -8 -9; + .port_info 0 /INPUT 1 "in0"; + .port_info 1 /INPUT 1 "in1"; + .port_info 2 /OUTPUT 1 "out"; +P_0x55cf9dbfd3f0 .param/l "BIT_WIDTH" 0 11 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dbfd430 .param/str "NAME" 0 11 3, "\000"; +P_0x55cf9dbfd470 .param/l "UUID" 0 11 2, C4<0001000110010100011100011110101011100000111001011000101110101010>; +L_0x55cf9dc4ffe0 .functor AND 1, L_0x55cf9dc4fb60, L_0x55cf9dc4fd10, C4<1>, C4<1>; +L_0x55cf9dc50190 .functor NOT 1, L_0x55cf9dc4ffe0, C4<0>, C4<0>, C4<0>; +v0x55cf9dbfd6c0_0 .net *"_ivl_0", 0 0, L_0x55cf9dc4ffe0; 1 drivers +v0x55cf9dbfd7c0_0 .net "in0", 0 0, L_0x55cf9dc4fb60; alias, 1 drivers +v0x55cf9dbfd8a0_0 .net "in1", 0 0, L_0x55cf9dc4fd10; alias, 1 drivers +v0x55cf9dbfd960_0 .net "out", 0 0, L_0x55cf9dc50190; alias, 1 drivers +S_0x55cf9dbfdac0 .scope module, "Nor_2" "TC_Nor" 25 13, 13 1 0, S_0x55cf9dbfc650; + .timescale -8 -9; + .port_info 0 /INPUT 1 "in0"; + .port_info 1 /INPUT 1 "in1"; + .port_info 2 /OUTPUT 1 "out"; +P_0x55cf9dbfdcd0 .param/l "BIT_WIDTH" 0 13 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dbfdd10 .param/str "NAME" 0 13 3, "\000"; +P_0x55cf9dbfdd50 .param/l "UUID" 0 13 2, C4<0000111010000010111010101000011000100100001011001100101000111001>; +L_0x55cf9dc4f620 .functor OR 1, L_0x55cf9dc4f3b0, L_0x55cf9dc4f310, C4<0>, C4<0>; +L_0x55cf9dc4f720 .functor NOT 1, L_0x55cf9dc4f620, C4<0>, C4<0>, C4<0>; +v0x55cf9dbfdf80_0 .net *"_ivl_0", 0 0, L_0x55cf9dc4f620; 1 drivers +v0x55cf9dbfe080_0 .net "in0", 0 0, L_0x55cf9dc4f3b0; alias, 1 drivers +v0x55cf9dbfe160_0 .net "in1", 0 0, L_0x55cf9dc4f310; alias, 1 drivers +v0x55cf9dbfe250_0 .net "out", 0 0, L_0x55cf9dc4f720; alias, 1 drivers +S_0x55cf9dbfe3a0 .scope module, "Nor_3" "TC_Nor" 25 14, 13 1 0, S_0x55cf9dbfc650; + .timescale -8 -9; + .port_info 0 /INPUT 1 "in0"; + .port_info 1 /INPUT 1 "in1"; + .port_info 2 /OUTPUT 1 "out"; +P_0x55cf9dbfe580 .param/l "BIT_WIDTH" 0 13 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dbfe5c0 .param/str "NAME" 0 13 3, "\000"; +P_0x55cf9dbfe600 .param/l "UUID" 0 13 2, C4<0011111001101010001000010001010010010101110010001101001101111001>; +L_0x55cf9dc4f790 .functor OR 1, L_0x55cf9dc4f230, L_0x55cf9dc4f190, C4<0>, C4<0>; +L_0x55cf9dc4f920 .functor NOT 1, L_0x55cf9dc4f790, C4<0>, C4<0>, C4<0>; +v0x55cf9dbfe850_0 .net *"_ivl_0", 0 0, L_0x55cf9dc4f790; 1 drivers +v0x55cf9dbfe950_0 .net "in0", 0 0, L_0x55cf9dc4f230; alias, 1 drivers +v0x55cf9dbfea30_0 .net "in1", 0 0, L_0x55cf9dc4f190; alias, 1 drivers +v0x55cf9dbfeb20_0 .net "out", 0 0, L_0x55cf9dc4f920; alias, 1 drivers +S_0x55cf9dbfec70 .scope module, "Nor_4" "TC_Nor" 25 15, 13 1 0, S_0x55cf9dbfc650; + .timescale -8 -9; + .port_info 0 /INPUT 1 "in0"; + .port_info 1 /INPUT 1 "in1"; + .port_info 2 /OUTPUT 1 "out"; +P_0x55cf9dbfeea0 .param/l "BIT_WIDTH" 0 13 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dbfeee0 .param/str "NAME" 0 13 3, "\000"; +P_0x55cf9dbfef20 .param/l "UUID" 0 13 2, C4<0010100100110001011010010100010111100110111110101100111011110100>; +L_0x55cf9dc4f9b0 .functor OR 1, L_0x55cf9dc4f060, L_0x55cf9dc4efc0, C4<0>, C4<0>; +L_0x55cf9dc4fb60 .functor NOT 1, L_0x55cf9dc4f9b0, C4<0>, C4<0>, C4<0>; +v0x55cf9dbff170_0 .net *"_ivl_0", 0 0, L_0x55cf9dc4f9b0; 1 drivers +v0x55cf9dbff270_0 .net "in0", 0 0, L_0x55cf9dc4f060; alias, 1 drivers +v0x55cf9dbff350_0 .net "in1", 0 0, L_0x55cf9dc4efc0; alias, 1 drivers +v0x55cf9dbff410_0 .net "out", 0 0, L_0x55cf9dc4fb60; alias, 1 drivers +S_0x55cf9dbff560 .scope module, "Nor_5" "TC_Nor" 25 16, 13 1 0, S_0x55cf9dbfc650; + .timescale -8 -9; + .port_info 0 /INPUT 1 "in0"; + .port_info 1 /INPUT 1 "in1"; + .port_info 2 /OUTPUT 1 "out"; +P_0x55cf9dbff740 .param/l "BIT_WIDTH" 0 13 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dbff780 .param/str "NAME" 0 13 3, "\000"; +P_0x55cf9dbff7c0 .param/l "UUID" 0 13 2, C4<0010100111011010011110011011000110011100001101101111101110011110>; +L_0x55cf9dc4fbf0 .functor OR 1, L_0x55cf9dc4ef20, L_0x55cf9dc4ee80, C4<0>, C4<0>; +L_0x55cf9dc4fd10 .functor NOT 1, L_0x55cf9dc4fbf0, C4<0>, C4<0>, C4<0>; +v0x55cf9dbffa10_0 .net *"_ivl_0", 0 0, L_0x55cf9dc4fbf0; 1 drivers +v0x55cf9dbffb10_0 .net "in0", 0 0, L_0x55cf9dc4ef20; alias, 1 drivers +v0x55cf9dbffbf0_0 .net "in1", 0 0, L_0x55cf9dc4ee80; alias, 1 drivers +v0x55cf9dbffce0_0 .net "out", 0 0, L_0x55cf9dc4fd10; alias, 1 drivers +S_0x55cf9dbffe30 .scope module, "Nor_8" "TC_Nor" 25 19, 13 1 0, S_0x55cf9dbfc650; + .timescale -8 -9; + .port_info 0 /INPUT 1 "in0"; + .port_info 1 /INPUT 1 "in1"; + .port_info 2 /OUTPUT 1 "out"; +P_0x55cf9dc00010 .param/l "BIT_WIDTH" 0 13 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dc00050 .param/str "NAME" 0 13 3, "\000"; +P_0x55cf9dc00090 .param/l "UUID" 0 13 2, C4<0010100111000001010111100011001000111110000100011100000111010011>; +L_0x55cf9dc50220 .functor OR 1, L_0x55cf9dc4ff50, L_0x55cf9dc50190, C4<0>, C4<0>; +L_0x55cf9dc503d0 .functor NOT 1, L_0x55cf9dc50220, C4<0>, C4<0>, C4<0>; +v0x55cf9dc002e0_0 .net *"_ivl_0", 0 0, L_0x55cf9dc50220; 1 drivers +v0x55cf9dc003e0_0 .net "in0", 0 0, L_0x55cf9dc4ff50; alias, 1 drivers +v0x55cf9dc004d0_0 .net "in1", 0 0, L_0x55cf9dc50190; alias, 1 drivers +v0x55cf9dc005d0_0 .net "out", 0 0, L_0x55cf9dc503d0; alias, 1 drivers +S_0x55cf9dc006f0 .scope module, "Or_11" "TC_Or" 25 22, 15 1 0, S_0x55cf9dbfc650; + .timescale -8 -9; + .port_info 0 /INPUT 1 "in0"; + .port_info 1 /INPUT 1 "in1"; + .port_info 2 /OUTPUT 1 "out"; +P_0x55cf9dc008d0 .param/l "BIT_WIDTH" 0 15 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dc00910 .param/str "NAME" 0 15 3, "\000"; +P_0x55cf9dc00950 .param/l "UUID" 0 15 2, C4<0001111000111011011110000011101100001100110001010001100110000000>; +L_0x55cf9dc50580 .functor OR 1, v0x55cf9dc03930_0, v0x55cf9dc03000_0, C4<0>, C4<0>; +v0x55cf9dc00ba0_0 .net "in0", 0 0, v0x55cf9dc03930_0; alias, 1 drivers +v0x55cf9dc00ca0_0 .net "in1", 0 0, v0x55cf9dc03000_0; alias, 1 drivers +v0x55cf9dc00d80_0 .net "out", 0 0, L_0x55cf9dc50580; alias, 1 drivers +S_0x55cf9dc00ef0 .scope module, "Splitter8_0" "TC_Splitter8" 25 11, 21 1 0, S_0x55cf9dbfc650; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /OUTPUT 1 "out0"; + .port_info 2 /OUTPUT 1 "out1"; + .port_info 3 /OUTPUT 1 "out2"; + .port_info 4 /OUTPUT 1 "out3"; + .port_info 5 /OUTPUT 1 "out4"; + .port_info 6 /OUTPUT 1 "out5"; + .port_info 7 /OUTPUT 1 "out6"; + .port_info 8 /OUTPUT 1 "out7"; +P_0x55cf9db88040 .param/str "NAME" 0 21 3, "\000"; +P_0x55cf9db88080 .param/l "UUID" 0 21 2, C4<0000000110100110101111001110001101111010100001101111110111101101>; +L_0x55cf9dc4ee10 .functor BUFZ 8, L_0x55cf9dc50a60, C4<00000000>, C4<00000000>, C4<00000000>; +v0x55cf9dc012a0_0 .net *"_ivl_10", 7 0, L_0x55cf9dc4ee10; 1 drivers +v0x55cf9dc013a0_0 .net "in", 7 0, L_0x55cf9dc50a60; alias, 1 drivers +v0x55cf9dc01480_0 .net "out0", 0 0, L_0x55cf9dc4ec10; alias, 1 drivers +v0x55cf9dc01550_0 .net "out1", 0 0, L_0x55cf9dc4eb70; alias, 1 drivers +v0x55cf9dc01610_0 .net "out2", 0 0, L_0x55cf9dc4ea90; alias, 1 drivers +v0x55cf9dc01720_0 .net "out3", 0 0, L_0x55cf9dc4e9f0; 1 drivers +v0x55cf9dc017e0_0 .net "out4", 0 0, L_0x55cf9dc4e950; 1 drivers +v0x55cf9dc018a0_0 .net "out5", 0 0, L_0x55cf9dc4e8b0; 1 drivers +v0x55cf9dc01960_0 .net "out6", 0 0, L_0x55cf9dc4e7c0; 1 drivers +v0x55cf9dc01a20_0 .net "out7", 0 0, L_0x55cf9dc4e720; 1 drivers +L_0x55cf9dc4e720 .part L_0x55cf9dc4ee10, 7, 1; +L_0x55cf9dc4e7c0 .part L_0x55cf9dc4ee10, 6, 1; +L_0x55cf9dc4e8b0 .part L_0x55cf9dc4ee10, 5, 1; +L_0x55cf9dc4e950 .part L_0x55cf9dc4ee10, 4, 1; +L_0x55cf9dc4e9f0 .part L_0x55cf9dc4ee10, 3, 1; +L_0x55cf9dc4ea90 .part L_0x55cf9dc4ee10, 2, 1; +L_0x55cf9dc4eb70 .part L_0x55cf9dc4ee10, 1, 1; +L_0x55cf9dc4ec10 .part L_0x55cf9dc4ee10, 0, 1; +S_0x55cf9dc01c00 .scope module, "Splitter8_1" "TC_Splitter8" 25 12, 21 1 0, S_0x55cf9dbfc650; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /OUTPUT 1 "out0"; + .port_info 2 /OUTPUT 1 "out1"; + .port_info 3 /OUTPUT 1 "out2"; + .port_info 4 /OUTPUT 1 "out3"; + .port_info 5 /OUTPUT 1 "out4"; + .port_info 6 /OUTPUT 1 "out5"; + .port_info 7 /OUTPUT 1 "out6"; + .port_info 8 /OUTPUT 1 "out7"; +P_0x55cf9dbd62f0 .param/str "NAME" 0 21 3, "\000"; +P_0x55cf9dbd6330 .param/l "UUID" 0 21 2, C4<0011100010001111111011000010101001000111011111101000001110101010>; +L_0x55cf9dc4f5b0 .functor BUFZ 8, L_0x55cf9dc50b80, C4<00000000>, C4<00000000>, C4<00000000>; +v0x55cf9dc01fd0_0 .net *"_ivl_10", 7 0, L_0x55cf9dc4f5b0; 1 drivers +v0x55cf9dc020d0_0 .net "in", 7 0, L_0x55cf9dc50b80; alias, 1 drivers +v0x55cf9dc021b0_0 .net "out0", 0 0, L_0x55cf9dc4f3b0; alias, 1 drivers +v0x55cf9dc02280_0 .net "out1", 0 0, L_0x55cf9dc4f310; alias, 1 drivers +v0x55cf9dc02350_0 .net "out2", 0 0, L_0x55cf9dc4f230; alias, 1 drivers +v0x55cf9dc02440_0 .net "out3", 0 0, L_0x55cf9dc4f190; alias, 1 drivers +v0x55cf9dc02510_0 .net "out4", 0 0, L_0x55cf9dc4f060; alias, 1 drivers +v0x55cf9dc025e0_0 .net "out5", 0 0, L_0x55cf9dc4efc0; alias, 1 drivers +v0x55cf9dc026b0_0 .net "out6", 0 0, L_0x55cf9dc4ef20; alias, 1 drivers +v0x55cf9dc02780_0 .net "out7", 0 0, L_0x55cf9dc4ee80; alias, 1 drivers +L_0x55cf9dc4ee80 .part L_0x55cf9dc4f5b0, 7, 1; +L_0x55cf9dc4ef20 .part L_0x55cf9dc4f5b0, 6, 1; +L_0x55cf9dc4efc0 .part L_0x55cf9dc4f5b0, 5, 1; +L_0x55cf9dc4f060 .part L_0x55cf9dc4f5b0, 4, 1; +L_0x55cf9dc4f190 .part L_0x55cf9dc4f5b0, 3, 1; +L_0x55cf9dc4f230 .part L_0x55cf9dc4f5b0, 2, 1; +L_0x55cf9dc4f310 .part L_0x55cf9dc4f5b0, 1, 1; +L_0x55cf9dc4f3b0 .part L_0x55cf9dc4f5b0, 0, 1; +S_0x55cf9dc02850 .scope module, "Switch1_10" "TC_Switch" 25 21, 16 1 0, S_0x55cf9dbfc650; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 1 "in"; + .port_info 2 /OUTPUT 1 "out"; +P_0x55cf9dc029e0 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dc02a20 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dc02a60 .param/l "UUID" 0 16 2, C4<0000110110011000110001001111001010001111001100010101011000000011>; +v0x55cf9dc02d50_0 .net "en", 0 0, L_0x55cf9dc4eb70; alias, 1 drivers +v0x55cf9dc02e40_0 .net "in", 0 0, L_0x55cf9dc4ee80; alias, 1 drivers +v0x55cf9dc02f30_0 .net "out", 0 0, v0x55cf9dc03000_0; alias, 1 drivers +v0x55cf9dc03000_0 .var "outval", 0 0; +E_0x55cf9dc02cd0 .event anyedge, v0x55cf9dbffbf0_0, v0x55cf9dc01550_0; +S_0x55cf9dc03140 .scope module, "Switch1_9" "TC_Switch" 25 20, 16 1 0, S_0x55cf9dbfc650; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 1 "in"; + .port_info 2 /OUTPUT 1 "out"; +P_0x55cf9dc03320 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dc03360 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dc033a0 .param/l "UUID" 0 16 2, C4<0000010000011100111110010011110100111001111011101001101111110110>; +v0x55cf9dc03670_0 .net "en", 0 0, L_0x55cf9dc4ec10; alias, 1 drivers +v0x55cf9dc03760_0 .net "in", 0 0, L_0x55cf9dc503d0; alias, 1 drivers +v0x55cf9dc03830_0 .net "out", 0 0, v0x55cf9dc03930_0; alias, 1 drivers +v0x55cf9dc03930_0 .var "outval", 0 0; +E_0x55cf9dc035f0 .event anyedge, v0x55cf9dc005d0_0, v0x55cf9dc01480_0; +S_0x55cf9dc03a50 .scope module, "Xor_12" "TC_Xor" 25 23, 23 1 0, S_0x55cf9dbfc650; + .timescale -8 -9; + .port_info 0 /INPUT 1 "in0"; + .port_info 1 /INPUT 1 "in1"; + .port_info 2 /OUTPUT 1 "out"; +P_0x55cf9dc03c30 .param/l "BIT_WIDTH" 0 23 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dc03c70 .param/str "NAME" 0 23 3, "\000"; +P_0x55cf9dc03cb0 .param/l "UUID" 0 23 2, C4<0010000101011101110100001111111001110101010111011011100001101110>; +L_0x55cf9dc50750 .functor XOR 1, L_0x55cf9dc4ea90, L_0x55cf9dc50580, C4<0>, C4<0>; +v0x55cf9dc03f00_0 .net "in0", 0 0, L_0x55cf9dc4ea90; alias, 1 drivers +v0x55cf9dc04010_0 .net "in1", 0 0, L_0x55cf9dc50580; alias, 1 drivers +v0x55cf9dc040e0_0 .net "out", 0 0, L_0x55cf9dc50750; alias, 1 drivers +S_0x55cf9dc05ef0 .scope module, "Counter8_34" "TC_Counter" 3 46, 26 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "save"; + .port_info 3 /INPUT 8 "in"; + .port_info 4 /OUTPUT 8 "out"; +P_0x55cf9dc060d0 .param/l "BIT_WIDTH" 0 26 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dc06110 .param/str "NAME" 0 26 3, "\000"; +P_0x55cf9dc06150 .param/l "UUID" 0 26 2, C4<0010110101001001011110010010000101000100111010110000000011001010>; +P_0x55cf9dc06190 .param/l "count" 0 26 5, C4<00000001>; +v0x55cf9dc06590_0 .net "clk", 0 0, v0x55cf9dc31950_0; alias, 1 drivers +v0x55cf9dc066a0_0 .net "in", 7 0, L_0x55cf9dc4c6a0; alias, 1 drivers +v0x55cf9dc06760_0 .var "out", 7 0; +v0x55cf9dc06800_0 .net "rst", 0 0, v0x55cf9dc32230_0; alias, 1 drivers +v0x55cf9dc068f0_0 .net "save", 0 0, L_0x55cf9dc4ad70; alias, 1 drivers +v0x55cf9dc069e0_0 .var "value", 7 0; +E_0x55cf9dc06510 .event posedge, v0x55cf9dbec3d0_0; +S_0x55cf9dc06b20 .scope module, "DEC_57" "DEC" 3 69, 27 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 8 "Instruction"; + .port_info 3 /OUTPUT 1 "IMM_EN"; + .port_info 4 /OUTPUT 1 "ALU_EN"; + .port_info 5 /OUTPUT 1 "COPY_EN"; + .port_info 6 /OUTPUT 1 "BRANCH_EN"; +P_0x55cf9dc049b0 .param/str "NAME" 0 27 3, "\000"; +P_0x55cf9dc049f0 .param/l "UUID" 0 27 2, C4<0011011011111111011111000011001110000101101101111000011101101101>; +L_0x55cf9dc4e250 .functor BUFZ 1, v0x55cf9dc07640_0, C4<0>, C4<0>, C4<0>; +L_0x55cf9dc4e350 .functor BUFZ 1, v0x55cf9dc07400_0, C4<0>, C4<0>, C4<0>; +L_0x55cf9dc4e430 .functor BUFZ 1, v0x55cf9dc074e0_0, C4<0>, C4<0>, C4<0>; +L_0x55cf9dc4e510 .functor BUFZ 8, L_0x55cf9dc49410, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x55cf9dc4e6b0 .functor BUFZ 1, v0x55cf9dc075a0_0, C4<0>, C4<0>, C4<0>; +v0x55cf9dc086a0_0 .net "ALU_EN", 0 0, L_0x55cf9dc4e430; alias, 1 drivers +v0x55cf9dc08780_0 .net "BRANCH_EN", 0 0, L_0x55cf9dc4e250; alias, 1 drivers +v0x55cf9dc08820_0 .net "COPY_EN", 0 0, L_0x55cf9dc4e6b0; alias, 1 drivers +v0x55cf9dc088c0_0 .net "IMM_EN", 0 0, L_0x55cf9dc4e350; alias, 1 drivers +v0x55cf9dc089a0_0 .net "Instruction", 7 0, L_0x55cf9dc49410; alias, 1 drivers +v0x55cf9dc08a60_0 .net "clk", 0 0, v0x55cf9dc31950_0; alias, 1 drivers +v0x55cf9dc08b00_0 .net "rst", 0 0, v0x55cf9dc32230_0; alias, 1 drivers +v0x55cf9dc08ba0_0 .net "wire_0", 0 0, v0x55cf9dc07640_0; 1 drivers +v0x55cf9dc08c40_0 .net "wire_1", 0 0, L_0x55cf9dc4da60; 1 drivers +v0x55cf9dc08d70_0 .net "wire_2", 0 0, v0x55cf9dc07400_0; 1 drivers +v0x55cf9dc08e30_0 .net "wire_3", 0 0, v0x55cf9dc074e0_0; 1 drivers +v0x55cf9dc08ed0_0 .net "wire_4", 7 0, L_0x55cf9dc4e510; 1 drivers +v0x55cf9dc08f70_0 .net "wire_5", 0 0, v0x55cf9dc075a0_0; 1 drivers +v0x55cf9dc09030_0 .net "wire_6", 0 0, L_0x55cf9dc4db00; 1 drivers +S_0x55cf9dc06f00 .scope module, "Decoder2_0" "TC_Decoder2" 27 13, 28 1 0, S_0x55cf9dc06b20; + .timescale -8 -9; + .port_info 0 /INPUT 1 "sel0"; + .port_info 1 /INPUT 1 "sel1"; + .port_info 2 /OUTPUT 1 "out0"; + .port_info 3 /OUTPUT 1 "out1"; + .port_info 4 /OUTPUT 1 "out2"; + .port_info 5 /OUTPUT 1 "out3"; +P_0x55cf9dc07100 .param/str "NAME" 0 28 3, "\000"; +P_0x55cf9dc07140 .param/l "UUID" 0 28 2, C4<0011101111000000011011010010010000011101101000110111110001011001>; +v0x55cf9dc07400_0 .var "out0", 0 0; +v0x55cf9dc074e0_0 .var "out1", 0 0; +v0x55cf9dc075a0_0 .var "out2", 0 0; +v0x55cf9dc07640_0 .var "out3", 0 0; +v0x55cf9dc07700_0 .net "sel0", 0 0, L_0x55cf9dc4db00; alias, 1 drivers +v0x55cf9dc07810_0 .net "sel1", 0 0, L_0x55cf9dc4da60; alias, 1 drivers +E_0x55cf9dc07380 .event anyedge, v0x55cf9dc07700_0, v0x55cf9dc07810_0; +S_0x55cf9dc079d0 .scope module, "Splitter8_1" "TC_Splitter8" 27 14, 21 1 0, S_0x55cf9dc06b20; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /OUTPUT 1 "out0"; + .port_info 2 /OUTPUT 1 "out1"; + .port_info 3 /OUTPUT 1 "out2"; + .port_info 4 /OUTPUT 1 "out3"; + .port_info 5 /OUTPUT 1 "out4"; + .port_info 6 /OUTPUT 1 "out5"; + .port_info 7 /OUTPUT 1 "out6"; + .port_info 8 /OUTPUT 1 "out7"; +P_0x55cf9dc07bd0 .param/str "NAME" 0 21 3, "\000"; +P_0x55cf9dc07c10 .param/l "UUID" 0 21 2, C4<0001001111010110100011111010101100010101100000101101010101010000>; +L_0x55cf9dc4e1e0 .functor BUFZ 8, L_0x55cf9dc4e510, C4<00000000>, C4<00000000>, C4<00000000>; +v0x55cf9dc07e80_0 .net *"_ivl_10", 7 0, L_0x55cf9dc4e1e0; 1 drivers +v0x55cf9dc07f80_0 .net "in", 7 0, L_0x55cf9dc4e510; alias, 1 drivers +v0x55cf9dc08020_0 .net "out0", 0 0, L_0x55cf9dc4dfe0; 1 drivers +v0x55cf9dc080c0_0 .net "out1", 0 0, L_0x55cf9dc4df40; 1 drivers +v0x55cf9dc08160_0 .net "out2", 0 0, L_0x55cf9dc4de60; 1 drivers +v0x55cf9dc08250_0 .net "out3", 0 0, L_0x55cf9dc4ddc0; 1 drivers +v0x55cf9dc082f0_0 .net "out4", 0 0, L_0x55cf9dc4dc90; 1 drivers +v0x55cf9dc08390_0 .net "out5", 0 0, L_0x55cf9dc4dbf0; 1 drivers +v0x55cf9dc08430_0 .net "out6", 0 0, L_0x55cf9dc4db00; alias, 1 drivers +v0x55cf9dc08560_0 .net "out7", 0 0, L_0x55cf9dc4da60; alias, 1 drivers +L_0x55cf9dc4da60 .part L_0x55cf9dc4e1e0, 7, 1; +L_0x55cf9dc4db00 .part L_0x55cf9dc4e1e0, 6, 1; +L_0x55cf9dc4dbf0 .part L_0x55cf9dc4e1e0, 5, 1; +L_0x55cf9dc4dc90 .part L_0x55cf9dc4e1e0, 4, 1; +L_0x55cf9dc4ddc0 .part L_0x55cf9dc4e1e0, 3, 1; +L_0x55cf9dc4de60 .part L_0x55cf9dc4e1e0, 2, 1; +L_0x55cf9dc4df40 .part L_0x55cf9dc4e1e0, 1, 1; +L_0x55cf9dc4dfe0 .part L_0x55cf9dc4e1e0, 0, 1; +S_0x55cf9dc09200 .scope module, "Decoder3_17" "TC_Decoder3" 3 29, 9 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "dis"; + .port_info 1 /INPUT 1 "sel0"; + .port_info 2 /INPUT 1 "sel1"; + .port_info 3 /INPUT 1 "sel2"; + .port_info 4 /OUTPUT 1 "out0"; + .port_info 5 /OUTPUT 1 "out1"; + .port_info 6 /OUTPUT 1 "out2"; + .port_info 7 /OUTPUT 1 "out3"; + .port_info 8 /OUTPUT 1 "out4"; + .port_info 9 /OUTPUT 1 "out5"; + .port_info 10 /OUTPUT 1 "out6"; + .port_info 11 /OUTPUT 1 "out7"; +P_0x55cf9dc093e0 .param/str "NAME" 0 9 3, "\000"; +P_0x55cf9dc09420 .param/l "UUID" 0 9 2, C4<0000010001110000011110101000011010111101100100000111111000101000>; +v0x55cf9dc096d0_0 .net "dis", 0 0, L_0x55cf9dc4ac00; alias, 1 drivers +v0x55cf9dc097b0_0 .var "out0", 0 0; +v0x55cf9dc09870_0 .var "out1", 0 0; +v0x55cf9dc09940_0 .var "out2", 0 0; +v0x55cf9dc09a00_0 .var "out3", 0 0; +v0x55cf9dc09b10_0 .var "out4", 0 0; +v0x55cf9dc09bd0_0 .var "out5", 0 0; +v0x55cf9dc09c90_0 .var "out6", 0 0; +v0x55cf9dc09d30_0 .var "out7", 0 0; +v0x55cf9dc09e60_0 .net "sel0", 0 0, L_0x55cf9dc49f20; alias, 1 drivers +v0x55cf9dc09f20_0 .net "sel1", 0 0, L_0x55cf9dc49dc0; alias, 1 drivers +v0x55cf9dc09fe0_0 .net "sel2", 0 0, L_0x55cf9dc49d20; alias, 1 drivers +E_0x55cf9dc06e10 .event anyedge, v0x55cf9dc09e60_0, v0x55cf9dc09f20_0, v0x55cf9dc09fe0_0, v0x55cf9dc096d0_0; +S_0x55cf9dc0a220 .scope module, "Decoder3_18" "TC_Decoder3" 3 30, 9 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "dis"; + .port_info 1 /INPUT 1 "sel0"; + .port_info 2 /INPUT 1 "sel1"; + .port_info 3 /INPUT 1 "sel2"; + .port_info 4 /OUTPUT 1 "out0"; + .port_info 5 /OUTPUT 1 "out1"; + .port_info 6 /OUTPUT 1 "out2"; + .port_info 7 /OUTPUT 1 "out3"; + .port_info 8 /OUTPUT 1 "out4"; + .port_info 9 /OUTPUT 1 "out5"; + .port_info 10 /OUTPUT 1 "out6"; + .port_info 11 /OUTPUT 1 "out7"; +P_0x55cf9dc0a3b0 .param/str "NAME" 0 9 3, "\000"; +P_0x55cf9dc0a3f0 .param/l "UUID" 0 9 2, C4<0011110101011100000010001001111010111010000000010100100001011111>; +v0x55cf9dc0a710_0 .net "dis", 0 0, L_0x55cf9dc4ac00; alias, 1 drivers +v0x55cf9dc0a800_0 .var "out0", 0 0; +v0x55cf9dc0a8a0_0 .var "out1", 0 0; +v0x55cf9dc0a970_0 .var "out2", 0 0; +v0x55cf9dc0aa30_0 .var "out3", 0 0; +v0x55cf9dc0ab40_0 .var "out4", 0 0; +v0x55cf9dc0ac00_0 .var "out5", 0 0; +v0x55cf9dc0acc0_0 .var "out6", 0 0; +v0x55cf9dc0ad60_0 .var "out7", 0 0; +v0x55cf9dc0ae90_0 .net "sel0", 0 0, L_0x55cf9dc4a140; alias, 1 drivers +v0x55cf9dc0af50_0 .net "sel1", 0 0, L_0x55cf9dc4a0a0; alias, 1 drivers +v0x55cf9dc0b010_0 .net "sel2", 0 0, L_0x55cf9dc49fc0; alias, 1 drivers +E_0x55cf9dc0a680 .event anyedge, v0x55cf9dc0ae90_0, v0x55cf9dc0af50_0, v0x55cf9dc0b010_0, v0x55cf9dc096d0_0; +S_0x55cf9dc0b250 .scope module, "Halt_1" "TC_Halt" 3 13, 29 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "en"; +P_0x55cf9dc0b3e0 .param/str "HALT_MESSAGE" 0 29 4, "\000"; +P_0x55cf9dc0b420 .param/str "NAME" 0 29 3, "\000"; +P_0x55cf9dc0b460 .param/l "UUID" 0 29 2, C4<0010100101001110011110000000001101010001010010111100010100111000>; +v0x55cf9dc0b720_0 .net "clk", 0 0, v0x55cf9dc31950_0; alias, 1 drivers +v0x55cf9dc0b870_0 .net "en", 0 0, L_0x55cf9dc322f0; alias, 1 drivers +v0x55cf9dc0b930_0 .net "rst", 0 0, v0x55cf9dc32230_0; alias, 1 drivers +E_0x55cf9dc0b6a0 .event negedge, v0x55cf9dbec3d0_0; +S_0x55cf9dc0baf0 .scope module, "LevelInputArch_5" "TC_Switch" 3 17, 16 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dc0bc80 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dc0bcc0 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dc0bd00 .param/l "UUID" 0 16 2, C4<0000011110111001101000011110000101010110000010100111001101000000>; +v0x55cf9dc0bf80_0 .net "en", 0 0, L_0x55cf9dc4b690; alias, 1 drivers +v0x55cf9dc0c070_0 .net "in", 7 0, v0x55cf9dc31b70_0; alias, 1 drivers +v0x55cf9dc0c130_0 .net "out", 7 0, v0x55cf9dc0c230_0; alias, 1 drivers +v0x55cf9dc0c230_0 .var "outval", 7 0; +E_0x55cf9dc0bf00 .event anyedge, v0x55cf9dc0c070_0, v0x55cf9dbf65b0_0; +S_0x55cf9dc0c370 .scope module, "LevelOutputArch_3" "TC_IOSwitch" 3 15, 30 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /INPUT 1 "en"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dc0c550 .param/l "BIT_WIDTH" 0 30 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dc0c590 .param/str "NAME" 0 30 3, "\000"; +P_0x55cf9dc0c5d0 .param/l "UUID" 0 30 2, C4<0010000010100111000000111111111110100011101101011011111111101011>; +L_0x55cf9dc323a0 .functor BUFZ 8, v0x55cf9dc0cb30_0, C4<00000000>, C4<00000000>, C4<00000000>; +v0x55cf9dc0c8a0_0 .net "en", 0 0, L_0x55cf9dc4b5e0; alias, 1 drivers +v0x55cf9dc0c990_0 .net "in", 7 0, L_0x55cf9dc49a90; alias, 1 drivers +v0x55cf9dc0ca60_0 .net "out", 7 0, L_0x55cf9dc323a0; alias, 1 drivers +v0x55cf9dc0cb30_0 .var "outval", 7 0; +E_0x55cf9dc0c820 .event anyedge, v0x55cf9dbf8ea0_0, v0x55cf9dbf5ed0_0; +S_0x55cf9dc0cc90 .scope module, "Maker16_20" "TC_Maker16" 3 32, 31 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in0"; + .port_info 1 /INPUT 8 "in1"; + .port_info 2 /OUTPUT 16 "out"; +P_0x55cf9dc0ce70 .param/str "NAME" 0 31 3, "\000"; +P_0x55cf9dc0ceb0 .param/l "UUID" 0 31 2, C4<0011101101000110110100010100010111111101110001101011011100010111>; +v0x55cf9dc0d060_0 .net "in0", 7 0, L_0x55cf9dc4cb40; alias, 1 drivers +v0x55cf9dc0d170_0 .net "in1", 7 0, L_0x55cf9dc4ce40; alias, 1 drivers +v0x55cf9dc0d240_0 .net "out", 15 0, L_0x55cf9dc4a2a0; alias, 1 drivers +L_0x55cf9dc4a2a0 .concat [ 8 8 0 0], L_0x55cf9dc4cb40, L_0x55cf9dc4ce40; +S_0x55cf9dc0d390 .scope module, "Maker16_50" "TC_Maker16" 3 62, 31 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in0"; + .port_info 1 /INPUT 8 "in1"; + .port_info 2 /OUTPUT 16 "out"; +P_0x55cf9dc0d570 .param/str "NAME" 0 31 3, "\000"; +P_0x55cf9dc0d5b0 .param/l "UUID" 0 31 2, C4<0000000000000100001100101001000001110000011110100010001001011000>; +v0x55cf9dc0d760_0 .net "in0", 7 0, L_0x55cf9dc4c050; alias, 1 drivers +v0x55cf9dc0d870_0 .net "in1", 7 0, L_0x55cf9dc4c190; alias, 1 drivers +v0x55cf9dc0d940_0 .net "out", 15 0, L_0x55cf9dc4c240; alias, 1 drivers +L_0x55cf9dc4c240 .concat [ 8 8 0 0], L_0x55cf9dc4c050, L_0x55cf9dc4c190; +S_0x55cf9dc0da90 .scope module, "Nand_28" "TC_Nand" 3 40, 11 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "in0"; + .port_info 1 /INPUT 1 "in1"; + .port_info 2 /OUTPUT 1 "out"; +P_0x55cf9dc0dc70 .param/l "BIT_WIDTH" 0 11 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dc0dcb0 .param/str "NAME" 0 11 3, "\000"; +P_0x55cf9dc0dcf0 .param/l "UUID" 0 11 2, C4<0011010110010000011000110001011100000000100101101011111111101001>; +L_0x55cf9dc4a970 .functor AND 1, v0x55cf9dc0ad60_0, v0x55cf9dc09d30_0, C4<1>, C4<1>; +L_0x55cf9dc4aa00 .functor NOT 1, L_0x55cf9dc4a970, C4<0>, C4<0>, C4<0>; +v0x55cf9dc0df40_0 .net *"_ivl_0", 0 0, L_0x55cf9dc4a970; 1 drivers +v0x55cf9dc0e040_0 .net "in0", 0 0, v0x55cf9dc0ad60_0; alias, 1 drivers +v0x55cf9dc0e130_0 .net "in1", 0 0, v0x55cf9dc09d30_0; alias, 1 drivers +v0x55cf9dc0e230_0 .net "out", 0 0, L_0x55cf9dc4aa00; alias, 1 drivers +S_0x55cf9dc0e340 .scope module, "Nor_42" "TC_Nor" 3 54, 13 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "in0"; + .port_info 1 /INPUT 1 "in1"; + .port_info 2 /OUTPUT 1 "out"; +P_0x55cf9dc0e520 .param/l "BIT_WIDTH" 0 13 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dc0e560 .param/str "NAME" 0 13 3, "\000"; +P_0x55cf9dc0e5a0 .param/l "UUID" 0 13 2, C4<0000000001100100000100001101110001010111101010110010010011110001>; +L_0x55cf9dc4b740 .functor OR 1, v0x55cf9dc09c90_0, v0x55cf9dc0acc0_0, C4<0>, C4<0>; +L_0x55cf9dc4b7d0 .functor NOT 1, L_0x55cf9dc4b740, C4<0>, C4<0>, C4<0>; +v0x55cf9dc0e7f0_0 .net *"_ivl_0", 0 0, L_0x55cf9dc4b740; 1 drivers +v0x55cf9dc0e8f0_0 .net "in0", 0 0, v0x55cf9dc09c90_0; alias, 1 drivers +v0x55cf9dc0ea00_0 .net "in1", 0 0, v0x55cf9dc0acc0_0; alias, 1 drivers +v0x55cf9dc0eaf0_0 .net "out", 0 0, L_0x55cf9dc4b7d0; alias, 1 drivers +S_0x55cf9dc0ec30 .scope module, "Not_2" "TC_Not" 3 14, 14 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "in"; + .port_info 1 /OUTPUT 1 "out"; +P_0x55cf9dc0ee10 .param/l "BIT_WIDTH" 0 14 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dc0ee50 .param/str "NAME" 0 14 3, "\000"; +P_0x55cf9dc0ee90 .param/l "UUID" 0 14 2, C4<0010001001001110011110100101010111100001010100101101110110100010>; +L_0x55cf9dc322f0 .functor NOT 1, L_0x55cf9dc4afc0, C4<0>, C4<0>, C4<0>; +v0x55cf9dc0f0d0_0 .net "in", 0 0, L_0x55cf9dc4afc0; alias, 1 drivers +v0x55cf9dc0f1b0_0 .net "out", 0 0, L_0x55cf9dc322f0; alias, 1 drivers +S_0x55cf9dc0f2c0 .scope module, "Or3_30" "TC_Or3" 3 42, 32 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "in0"; + .port_info 1 /INPUT 1 "in1"; + .port_info 2 /INPUT 1 "in2"; + .port_info 3 /OUTPUT 1 "out"; +P_0x55cf9dc0f4a0 .param/l "BIT_WIDTH" 0 32 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dc0f4e0 .param/str "NAME" 0 32 3, "\000"; +P_0x55cf9dc0f520 .param/l "UUID" 0 32 2, C4<0011011110101010000111000001010010011101001101001101010001010011>; +L_0x55cf9dc4ab70 .functor OR 1, L_0x55cf9dc4e350, L_0x55cf9dc4e430, C4<0>, C4<0>; +L_0x55cf9dc4ac00 .functor OR 1, L_0x55cf9dc4ab70, L_0x55cf9dc4e250, C4<0>, C4<0>; +v0x55cf9dc0f730_0 .net *"_ivl_0", 0 0, L_0x55cf9dc4ab70; 1 drivers +v0x55cf9dc0f830_0 .net "in0", 0 0, L_0x55cf9dc4e350; alias, 1 drivers +v0x55cf9dc0f920_0 .net "in1", 0 0, L_0x55cf9dc4e430; alias, 1 drivers +v0x55cf9dc0fa40_0 .net "in2", 0 0, L_0x55cf9dc4e250; alias, 1 drivers +v0x55cf9dc0fb30_0 .net "out", 0 0, L_0x55cf9dc4ac00; alias, 1 drivers +S_0x55cf9dc0fd10 .scope module, "Or_26" "TC_Or" 3 38, 15 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "in0"; + .port_info 1 /INPUT 1 "in1"; + .port_info 2 /OUTPUT 1 "out"; +P_0x55cf9dc0fef0 .param/l "BIT_WIDTH" 0 15 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dc0ff30 .param/str "NAME" 0 15 3, "\000"; +P_0x55cf9dc0ff70 .param/l "UUID" 0 15 2, C4<0011110000101101000001101001111010010000001101000010101110001100>; +L_0x55cf9dc4a670 .functor OR 1, L_0x55cf9dc4e250, L_0x55cf9dc4e350, C4<0>, C4<0>; +v0x55cf9dc101e0_0 .net "in0", 0 0, L_0x55cf9dc4e250; alias, 1 drivers +v0x55cf9dc102c0_0 .net "in1", 0 0, L_0x55cf9dc4e350; alias, 1 drivers +v0x55cf9dc103d0_0 .net "out", 0 0, L_0x55cf9dc4a670; alias, 1 drivers +S_0x55cf9dc10510 .scope module, "Program8_1_4" "TC_Program8_1" 3 16, 33 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 8 "address"; + .port_info 3 /OUTPUT 8 "out"; +P_0x55cf9dc106f0 .param/str "ARG_SIG" 0 33 6, "outport_test=%s"; +P_0x55cf9dc10730 .param/str "DEFAULT_FILE_NAME" 0 33 5, "outport_test.bin"; +P_0x55cf9dc10770 .param/l "MAX_WORD_COUNT" 0 33 4, +C4<00000000000000000000000100000000>; +P_0x55cf9dc107b0 .param/str "NAME" 0 33 3, "\000"; +P_0x55cf9dc107f0 .param/l "UUID" 0 33 2, C4<0010000000110001011000010110001000011001011110100101000101111000>; +v0x55cf9dc10be0_0 .net "address", 7 0, v0x55cf9dc06760_0; alias, 1 drivers +v0x55cf9dc10d10_0 .net "clk", 0 0, v0x55cf9dc31950_0; alias, 1 drivers +v0x55cf9dc10dd0_0 .var/i "fd", 31 0; +v0x55cf9dc10e70_0 .var "hexfile", 8192 0; +v0x55cf9dc10f50_0 .var/i "i", 31 0; +v0x55cf9dc11080 .array "mem", 255 0, 7 0; +v0x55cf9dc11140_0 .var "out", 7 0; +v0x55cf9dc11200_0 .net "rst", 0 0, v0x55cf9dc32230_0; alias, 1 drivers +E_0x55cf9dc10b60 .event anyedge, v0x55cf9dbec490_0, v0x55cf9dbf9b60_0; +S_0x55cf9dc11300 .scope module, "Ram_7" "TC_Ram" 3 19, 34 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "load"; + .port_info 3 /INPUT 1 "save"; + .port_info 4 /INPUT 32 "address"; + .port_info 5 /INPUT 64 "in0"; + .port_info 6 /INPUT 64 "in1"; + .port_info 7 /INPUT 64 "in2"; + .port_info 8 /INPUT 64 "in3"; + .port_info 9 /OUTPUT 64 "out0"; + .port_info 10 /OUTPUT 64 "out1"; + .port_info 11 /OUTPUT 64 "out2"; + .port_info 12 /OUTPUT 64 "out3"; +P_0x55cf9dbd0600 .param/str "NAME" 0 34 3, "\000"; +P_0x55cf9dbd0640 .param/l "UUID" 0 34 2, C4<0001011100010000100001001011111110110000111001001111000000110110>; +P_0x55cf9dbd0680 .param/l "WORD_COUNT" 0 34 5, C4<0000000000000000000000000000000000000000000000000000000001000000>; +P_0x55cf9dbd06c0 .param/l "WORD_WIDTH" 0 34 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +L_0x7fcf8ba884e0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55cf9dc11b60_0 .net "address", 31 0, L_0x7fcf8ba884e0; 1 drivers +v0x55cf9dc11c60_0 .net "clk", 0 0, v0x55cf9dc31950_0; alias, 1 drivers +v0x55cf9dc11d20_0 .var/i "i", 31 0; +L_0x7fcf8ba88528 .functor BUFT 1, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55cf9dc11dc0_0 .net "in0", 63 0, L_0x7fcf8ba88528; 1 drivers +L_0x7fcf8ba88570 .functor BUFT 1, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55cf9dc11ea0_0 .net "in1", 63 0, L_0x7fcf8ba88570; 1 drivers +L_0x7fcf8ba885b8 .functor BUFT 1, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55cf9dc11fd0_0 .net "in2", 63 0, L_0x7fcf8ba885b8; 1 drivers +L_0x7fcf8ba88600 .functor BUFT 1, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55cf9dc120b0_0 .net "in3", 63 0, L_0x7fcf8ba88600; 1 drivers +L_0x7fcf8ba88450 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55cf9dc12190_0 .net "load", 0 0, L_0x7fcf8ba88450; 1 drivers +v0x55cf9dc12250 .array "mem", 64 0, 7 0; +v0x55cf9dc12310_0 .var "out0", 63 0; +v0x55cf9dc123f0_0 .var "out1", 63 0; +v0x55cf9dc124d0_0 .var "out2", 63 0; +v0x55cf9dc125b0_0 .var "out3", 63 0; +v0x55cf9dc12690_0 .net "rst", 0 0, v0x55cf9dc32230_0; alias, 1 drivers +L_0x7fcf8ba88498 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55cf9dc12730_0 .net "save", 0 0, L_0x7fcf8ba88498; 1 drivers +S_0x55cf9dc118e0 .scope generate, "genblk1" "genblk1" 34 33, 34 33 0, S_0x55cf9dc11300; + .timescale -8 -9; +E_0x55cf9dc11ae0 .event anyedge, v0x55cf9dc12190_0, v0x55cf9dbec490_0, v0x55cf9dc11b60_0; +S_0x55cf9dc12a00 .scope module, "RegisterPlus_51" "RegisterPlus" 3 63, 35 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "Load"; + .port_info 3 /INPUT 8 "Save_value"; + .port_info 4 /INPUT 1 "Save"; + .port_info 5 /OUTPUT 8 "Always_output"; + .port_info 6 /OUTPUT 8 "Output"; +P_0x55cf9dc12b90 .param/str "NAME" 0 35 3, "\000"; +P_0x55cf9dc12bd0 .param/l "UUID" 0 35 2, C4<0010010011110000011110001010010111100000000111001010011100111011>; +L_0x55cf9dc4c560 .functor BUFZ 8, L_0x55cf9dc50da0, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x55cf9dc4c610 .functor BUFZ 1, v0x55cf9dc097b0_0, C4<0>, C4<0>, C4<0>; +L_0x55cf9dc4c6a0 .functor BUFZ 8, v0x55cf9dc14600_0, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x55cf9dc4c730 .functor BUFZ 1, L_0x55cf9dc4a360, C4<0>, C4<0>, C4<0>; +v0x55cf9dc14ae0_0 .net "Always_output", 7 0, L_0x55cf9dc4c6a0; alias, 1 drivers +v0x55cf9dc14c10_0 .net "Load", 0 0, v0x55cf9dc097b0_0; alias, 1 drivers +v0x55cf9dc14cd0_0 .net "Output", 7 0, v0x55cf9dc13c80_0; alias, 1 drivers +v0x55cf9dc14da0_0 .net "Save", 0 0, L_0x55cf9dc4a360; alias, 1 drivers +v0x55cf9dc14e40_0 .net "Save_value", 7 0, L_0x55cf9dc50da0; alias, 1 drivers +v0x55cf9dc14f70_0 .net "clk", 0 0, v0x55cf9dc31950_0; alias, 1 drivers +v0x55cf9dc15010_0 .net "rst", 0 0, v0x55cf9dc32230_0; alias, 1 drivers +v0x55cf9dc151c0_0 .net "wire_0", 7 0, L_0x55cf9dc4c560; 1 drivers +v0x55cf9dc15280_0 .net "wire_1", 0 0, L_0x55cf9dc4c610; 1 drivers +L_0x7fcf8ba88648 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +v0x55cf9dc15350_0 .net "wire_2", 0 0, L_0x7fcf8ba88648; 1 drivers +v0x55cf9dc153f0_0 .net "wire_3", 7 0, v0x55cf9dc14600_0; 1 drivers +v0x55cf9dc15500_0 .net "wire_4", 0 0, L_0x55cf9dc4c730; 1 drivers +S_0x55cf9dc12e20 .scope module, "On_1" "TC_Constant" 35 14, 8 2 0, S_0x55cf9dc12a00; + .timescale -8 -9; + .port_info 0 /OUTPUT 1 "out"; +P_0x55cf9dc06230 .param/l "BIT_WIDTH" 0 8 5, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dc06270 .param/str "NAME" 0 8 4, "\000"; +P_0x55cf9dc062b0 .param/l "UUID" 0 8 3, C4<0010010011110000011110001010010111100000000111001010011100111001>; +P_0x55cf9dc062f0 .param/l "value" 0 8 6, C4<1>; +v0x55cf9dc13390_0 .net "out", 0 0, L_0x7fcf8ba88648; alias, 1 drivers +S_0x55cf9dc134d0 .scope module, "Output8z_2" "TC_Switch" 35 15, 16 1 0, S_0x55cf9dc12a00; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dc136b0 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dc136f0 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dc13730 .param/l "UUID" 0 16 2, C4<0001010100111001001011000010101111001110110100101000010101110101>; +v0x55cf9dc13a00_0 .net "en", 0 0, L_0x55cf9dc4c610; alias, 1 drivers +v0x55cf9dc13ae0_0 .net "in", 7 0, v0x55cf9dc14600_0; alias, 1 drivers +v0x55cf9dc13bc0_0 .net "out", 7 0, v0x55cf9dc13c80_0; alias, 1 drivers +v0x55cf9dc13c80_0 .var "outval", 7 0; +E_0x55cf9dc13980 .event anyedge, v0x55cf9dc13ae0_0, v0x55cf9dc13a00_0; +S_0x55cf9dc13de0 .scope module, "Register8_0" "TC_Register" 35 13, 36 1 0, S_0x55cf9dc12a00; + .timescale -8 -9; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "load"; + .port_info 3 /INPUT 1 "save"; + .port_info 4 /INPUT 8 "in"; + .port_info 5 /OUTPUT 8 "out"; +P_0x55cf9dc13fc0 .param/l "BIT_WIDTH" 0 36 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dc14000 .param/str "NAME" 0 36 3, "\000"; +P_0x55cf9dc14040 .param/l "UUID" 0 36 2, C4<0010010011110000011110001010010111100000000111001010011100111010>; +v0x55cf9dc14360_0 .net "clk", 0 0, v0x55cf9dc31950_0; alias, 1 drivers +v0x55cf9dc14420_0 .net "in", 7 0, L_0x55cf9dc4c560; alias, 1 drivers +v0x55cf9dc14500_0 .net "load", 0 0, L_0x7fcf8ba88648; alias, 1 drivers +v0x55cf9dc14600_0 .var "out", 7 0; +v0x55cf9dc146d0_0 .var "reset", 0 0; +v0x55cf9dc147c0_0 .net "rst", 0 0, v0x55cf9dc32230_0; alias, 1 drivers +v0x55cf9dc14860_0 .net "save", 0 0, L_0x55cf9dc4c730; alias, 1 drivers +v0x55cf9dc14900_0 .var "value", 7 0; +E_0x55cf9dc14300/0 .event negedge, v0x55cf9dc13390_0; +E_0x55cf9dc14300/1 .event posedge, v0x55cf9dc13390_0; +E_0x55cf9dc14300 .event/or E_0x55cf9dc14300/0, E_0x55cf9dc14300/1; +S_0x55cf9dc15680 .scope module, "RegisterPlus_52" "RegisterPlus" 3 64, 35 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "Load"; + .port_info 3 /INPUT 8 "Save_value"; + .port_info 4 /INPUT 1 "Save"; + .port_info 5 /OUTPUT 8 "Always_output"; + .port_info 6 /OUTPUT 8 "Output"; +P_0x55cf9dc0b7e0 .param/str "NAME" 0 35 3, "\000"; +P_0x55cf9dc0b820 .param/l "UUID" 0 35 2, C4<0001111000000101010010101010010001011100001101111101100000100100>; +L_0x55cf9dc4c8f0 .functor BUFZ 8, L_0x55cf9dc50da0, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x55cf9dc4cab0 .functor BUFZ 1, v0x55cf9dc09870_0, C4<0>, C4<0>, C4<0>; +L_0x55cf9dc4cb40 .functor BUFZ 8, v0x55cf9dc17340_0, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x55cf9dc4cbd0 .functor BUFZ 1, v0x55cf9dc0a8a0_0, C4<0>, C4<0>, C4<0>; +v0x55cf9dc17820_0 .net "Always_output", 7 0, L_0x55cf9dc4cb40; alias, 1 drivers +v0x55cf9dc17950_0 .net "Load", 0 0, v0x55cf9dc09870_0; alias, 1 drivers +v0x55cf9dc17a10_0 .net "Output", 7 0, v0x55cf9dc16990_0; alias, 1 drivers +v0x55cf9dc17ae0_0 .net "Save", 0 0, v0x55cf9dc0a8a0_0; alias, 1 drivers +v0x55cf9dc17bb0_0 .net "Save_value", 7 0, L_0x55cf9dc50da0; alias, 1 drivers +v0x55cf9dc17ca0_0 .net "clk", 0 0, v0x55cf9dc31950_0; alias, 1 drivers +v0x55cf9dc17d40_0 .net "rst", 0 0, v0x55cf9dc32230_0; alias, 1 drivers +v0x55cf9dc17de0_0 .net "wire_0", 7 0, L_0x55cf9dc4c8f0; 1 drivers +v0x55cf9dc17eb0_0 .net "wire_1", 0 0, L_0x55cf9dc4cab0; 1 drivers +L_0x7fcf8ba88690 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +v0x55cf9dc18010_0 .net "wire_2", 0 0, L_0x7fcf8ba88690; 1 drivers +v0x55cf9dc180b0_0 .net "wire_3", 7 0, v0x55cf9dc17340_0; 1 drivers +v0x55cf9dc181a0_0 .net "wire_4", 0 0, L_0x55cf9dc4cbd0; 1 drivers +S_0x55cf9dc15b30 .scope module, "On_1" "TC_Constant" 35 14, 8 2 0, S_0x55cf9dc15680; + .timescale -8 -9; + .port_info 0 /OUTPUT 1 "out"; +P_0x55cf9dc15920 .param/l "BIT_WIDTH" 0 8 5, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dc15960 .param/str "NAME" 0 8 4, "\000"; +P_0x55cf9dc159a0 .param/l "UUID" 0 8 3, C4<0001111000000101010010101010010001011100001101111101100000100110>; +P_0x55cf9dc159e0 .param/l "value" 0 8 6, C4<1>; +v0x55cf9dc160a0_0 .net "out", 0 0, L_0x7fcf8ba88690; alias, 1 drivers +S_0x55cf9dc161e0 .scope module, "Output8z_2" "TC_Switch" 35 15, 16 1 0, S_0x55cf9dc15680; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dc163c0 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dc16400 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dc16440 .param/l "UUID" 0 16 2, C4<0010111111001100000111100010101001110010111110011111101001101010>; +v0x55cf9dc16710_0 .net "en", 0 0, L_0x55cf9dc4cab0; alias, 1 drivers +v0x55cf9dc167f0_0 .net "in", 7 0, v0x55cf9dc17340_0; alias, 1 drivers +v0x55cf9dc168d0_0 .net "out", 7 0, v0x55cf9dc16990_0; alias, 1 drivers +v0x55cf9dc16990_0 .var "outval", 7 0; +E_0x55cf9dc16690 .event anyedge, v0x55cf9dc167f0_0, v0x55cf9dc16710_0; +S_0x55cf9dc16af0 .scope module, "Register8_0" "TC_Register" 35 13, 36 1 0, S_0x55cf9dc15680; + .timescale -8 -9; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "load"; + .port_info 3 /INPUT 1 "save"; + .port_info 4 /INPUT 8 "in"; + .port_info 5 /OUTPUT 8 "out"; +P_0x55cf9dc16d00 .param/l "BIT_WIDTH" 0 36 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dc16d40 .param/str "NAME" 0 36 3, "\000"; +P_0x55cf9dc16d80 .param/l "UUID" 0 36 2, C4<0001111000000101010010101010010001011100001101111101100000100101>; +v0x55cf9dc170a0_0 .net "clk", 0 0, v0x55cf9dc31950_0; alias, 1 drivers +v0x55cf9dc17160_0 .net "in", 7 0, L_0x55cf9dc4c8f0; alias, 1 drivers +v0x55cf9dc17240_0 .net "load", 0 0, L_0x7fcf8ba88690; alias, 1 drivers +v0x55cf9dc17340_0 .var "out", 7 0; +v0x55cf9dc17410_0 .var "reset", 0 0; +v0x55cf9dc17500_0 .net "rst", 0 0, v0x55cf9dc32230_0; alias, 1 drivers +v0x55cf9dc175a0_0 .net "save", 0 0, L_0x55cf9dc4cbd0; alias, 1 drivers +v0x55cf9dc17640_0 .var "value", 7 0; +E_0x55cf9dc17040/0 .event negedge, v0x55cf9dc160a0_0; +E_0x55cf9dc17040/1 .event posedge, v0x55cf9dc160a0_0; +E_0x55cf9dc17040 .event/or E_0x55cf9dc17040/0, E_0x55cf9dc17040/1; +S_0x55cf9dc18320 .scope module, "RegisterPlus_53" "RegisterPlus" 3 65, 35 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "Load"; + .port_info 3 /INPUT 8 "Save_value"; + .port_info 4 /INPUT 1 "Save"; + .port_info 5 /OUTPUT 8 "Always_output"; + .port_info 6 /OUTPUT 8 "Output"; +P_0x55cf9dc18500 .param/str "NAME" 0 35 3, "\000"; +P_0x55cf9dc18540 .param/l "UUID" 0 35 2, C4<0001001010110011101110111110000001011100100110000010000110011101>; +L_0x55cf9dc4cd00 .functor BUFZ 8, L_0x55cf9dc50da0, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x55cf9dc4cdb0 .functor BUFZ 1, v0x55cf9dc09940_0, C4<0>, C4<0>, C4<0>; +L_0x55cf9dc4ce40 .functor BUFZ 8, v0x55cf9dc19f60_0, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x55cf9dc4ced0 .functor BUFZ 1, v0x55cf9dc0a970_0, C4<0>, C4<0>, C4<0>; +v0x55cf9dc1a440_0 .net "Always_output", 7 0, L_0x55cf9dc4ce40; alias, 1 drivers +v0x55cf9dc1a570_0 .net "Load", 0 0, v0x55cf9dc09940_0; alias, 1 drivers +v0x55cf9dc1a630_0 .net "Output", 7 0, v0x55cf9dc195b0_0; alias, 1 drivers +v0x55cf9dc1a700_0 .net "Save", 0 0, v0x55cf9dc0a970_0; alias, 1 drivers +v0x55cf9dc1a7d0_0 .net "Save_value", 7 0, L_0x55cf9dc50da0; alias, 1 drivers +v0x55cf9dc1a910_0 .net "clk", 0 0, v0x55cf9dc31950_0; alias, 1 drivers +v0x55cf9dc1a9b0_0 .net "rst", 0 0, v0x55cf9dc32230_0; alias, 1 drivers +v0x55cf9dc1aa50_0 .net "wire_0", 7 0, L_0x55cf9dc4cd00; 1 drivers +v0x55cf9dc1aaf0_0 .net "wire_1", 0 0, L_0x55cf9dc4cdb0; 1 drivers +L_0x7fcf8ba886d8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +v0x55cf9dc1ac20_0 .net "wire_2", 0 0, L_0x7fcf8ba886d8; 1 drivers +v0x55cf9dc1acc0_0 .net "wire_3", 7 0, v0x55cf9dc19f60_0; 1 drivers +v0x55cf9dc1add0_0 .net "wire_4", 0 0, L_0x55cf9dc4ced0; 1 drivers +S_0x55cf9dc18750 .scope module, "On_1" "TC_Constant" 35 14, 8 2 0, S_0x55cf9dc18320; + .timescale -8 -9; + .port_info 0 /OUTPUT 1 "out"; +P_0x55cf9dc15d80 .param/l "BIT_WIDTH" 0 8 5, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dc15dc0 .param/str "NAME" 0 8 4, "\000"; +P_0x55cf9dc15e00 .param/l "UUID" 0 8 3, C4<0001001010110011101110111110000001011100100110000010000110011111>; +P_0x55cf9dc15e40 .param/l "value" 0 8 6, C4<1>; +v0x55cf9dc18cc0_0 .net "out", 0 0, L_0x7fcf8ba886d8; alias, 1 drivers +S_0x55cf9dc18e00 .scope module, "Output8z_2" "TC_Switch" 35 15, 16 1 0, S_0x55cf9dc18320; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dc18fe0 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dc19020 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dc19060 .param/l "UUID" 0 16 2, C4<0010001101111010111011110110111001110010010101100000001111010011>; +v0x55cf9dc19330_0 .net "en", 0 0, L_0x55cf9dc4cdb0; alias, 1 drivers +v0x55cf9dc19410_0 .net "in", 7 0, v0x55cf9dc19f60_0; alias, 1 drivers +v0x55cf9dc194f0_0 .net "out", 7 0, v0x55cf9dc195b0_0; alias, 1 drivers +v0x55cf9dc195b0_0 .var "outval", 7 0; +E_0x55cf9dc192b0 .event anyedge, v0x55cf9dc19410_0, v0x55cf9dc19330_0; +S_0x55cf9dc19710 .scope module, "Register8_0" "TC_Register" 35 13, 36 1 0, S_0x55cf9dc18320; + .timescale -8 -9; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "load"; + .port_info 3 /INPUT 1 "save"; + .port_info 4 /INPUT 8 "in"; + .port_info 5 /OUTPUT 8 "out"; +P_0x55cf9dc19920 .param/l "BIT_WIDTH" 0 36 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dc19960 .param/str "NAME" 0 36 3, "\000"; +P_0x55cf9dc199a0 .param/l "UUID" 0 36 2, C4<0001001010110011101110111110000001011100100110000010000110011100>; +v0x55cf9dc19cc0_0 .net "clk", 0 0, v0x55cf9dc31950_0; alias, 1 drivers +v0x55cf9dc19d80_0 .net "in", 7 0, L_0x55cf9dc4cd00; alias, 1 drivers +v0x55cf9dc19e60_0 .net "load", 0 0, L_0x7fcf8ba886d8; alias, 1 drivers +v0x55cf9dc19f60_0 .var "out", 7 0; +v0x55cf9dc1a030_0 .var "reset", 0 0; +v0x55cf9dc1a120_0 .net "rst", 0 0, v0x55cf9dc32230_0; alias, 1 drivers +v0x55cf9dc1a1c0_0 .net "save", 0 0, L_0x55cf9dc4ced0; alias, 1 drivers +v0x55cf9dc1a260_0 .var "value", 7 0; +E_0x55cf9dc19c60/0 .event negedge, v0x55cf9dc18cc0_0; +E_0x55cf9dc19c60/1 .event posedge, v0x55cf9dc18cc0_0; +E_0x55cf9dc19c60 .event/or E_0x55cf9dc19c60/0, E_0x55cf9dc19c60/1; +S_0x55cf9dc1af50 .scope module, "RegisterPlus_54" "RegisterPlus" 3 66, 35 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "Load"; + .port_info 3 /INPUT 8 "Save_value"; + .port_info 4 /INPUT 1 "Save"; + .port_info 5 /OUTPUT 8 "Always_output"; + .port_info 6 /OUTPUT 8 "Output"; +P_0x55cf9dc1b130 .param/str "NAME" 0 35 3, "\000"; +P_0x55cf9dc1b170 .param/l "UUID" 0 35 2, C4<0010101111110011001001010000101000111000001001011101000100000001>; +L_0x55cf9dc4d000 .functor BUFZ 8, L_0x55cf9dc50da0, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x55cf9dc4d0b0 .functor BUFZ 1, v0x55cf9dc09a00_0, C4<0>, C4<0>, C4<0>; +L_0x55cf9dc4d140 .functor BUFZ 8, v0x55cf9dc1cb90_0, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x55cf9dc4d1d0 .functor BUFZ 1, L_0x55cf9dc4a7b0, C4<0>, C4<0>, C4<0>; +v0x55cf9dc1d070_0 .net "Always_output", 7 0, L_0x55cf9dc4d140; alias, 1 drivers +v0x55cf9dc1d1a0_0 .net "Load", 0 0, v0x55cf9dc09a00_0; alias, 1 drivers +v0x55cf9dc1d260_0 .net "Output", 7 0, v0x55cf9dc1c1e0_0; alias, 1 drivers +v0x55cf9dc1d330_0 .net "Save", 0 0, L_0x55cf9dc4a7b0; alias, 1 drivers +v0x55cf9dc1d3d0_0 .net "Save_value", 7 0, L_0x55cf9dc50da0; alias, 1 drivers +v0x55cf9dc1d4e0_0 .net "clk", 0 0, v0x55cf9dc31950_0; alias, 1 drivers +v0x55cf9dc1d580_0 .net "rst", 0 0, v0x55cf9dc32230_0; alias, 1 drivers +v0x55cf9dc1d620_0 .net "wire_0", 7 0, L_0x55cf9dc4d000; 1 drivers +v0x55cf9dc1d6e0_0 .net "wire_1", 0 0, L_0x55cf9dc4d0b0; 1 drivers +L_0x7fcf8ba88720 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +v0x55cf9dc1d840_0 .net "wire_2", 0 0, L_0x7fcf8ba88720; 1 drivers +v0x55cf9dc1d8e0_0 .net "wire_3", 7 0, v0x55cf9dc1cb90_0; 1 drivers +v0x55cf9dc1d9f0_0 .net "wire_4", 0 0, L_0x55cf9dc4d1d0; 1 drivers +S_0x55cf9dc1b380 .scope module, "On_1" "TC_Constant" 35 14, 8 2 0, S_0x55cf9dc1af50; + .timescale -8 -9; + .port_info 0 /OUTPUT 1 "out"; +P_0x55cf9dc189a0 .param/l "BIT_WIDTH" 0 8 5, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dc189e0 .param/str "NAME" 0 8 4, "\000"; +P_0x55cf9dc18a20 .param/l "UUID" 0 8 3, C4<0010101111110011001001010000101000111000001001011101000100000011>; +P_0x55cf9dc18a60 .param/l "value" 0 8 6, C4<1>; +v0x55cf9dc1b8f0_0 .net "out", 0 0, L_0x7fcf8ba88720; alias, 1 drivers +S_0x55cf9dc1ba30 .scope module, "Output8z_2" "TC_Switch" 35 15, 16 1 0, S_0x55cf9dc1af50; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dc1bc10 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dc1bc50 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dc1bc90 .param/l "UUID" 0 16 2, C4<0001101000111010011100011000010000010110111010111111001101001111>; +v0x55cf9dc1bf60_0 .net "en", 0 0, L_0x55cf9dc4d0b0; alias, 1 drivers +v0x55cf9dc1c040_0 .net "in", 7 0, v0x55cf9dc1cb90_0; alias, 1 drivers +v0x55cf9dc1c120_0 .net "out", 7 0, v0x55cf9dc1c1e0_0; alias, 1 drivers +v0x55cf9dc1c1e0_0 .var "outval", 7 0; +E_0x55cf9dc1bee0 .event anyedge, v0x55cf9dc1c040_0, v0x55cf9dc1bf60_0; +S_0x55cf9dc1c340 .scope module, "Register8_0" "TC_Register" 35 13, 36 1 0, S_0x55cf9dc1af50; + .timescale -8 -9; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "load"; + .port_info 3 /INPUT 1 "save"; + .port_info 4 /INPUT 8 "in"; + .port_info 5 /OUTPUT 8 "out"; +P_0x55cf9dc1c550 .param/l "BIT_WIDTH" 0 36 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dc1c590 .param/str "NAME" 0 36 3, "\000"; +P_0x55cf9dc1c5d0 .param/l "UUID" 0 36 2, C4<0010101111110011001001010000101000111000001001011101000100000000>; +v0x55cf9dc1c8f0_0 .net "clk", 0 0, v0x55cf9dc31950_0; alias, 1 drivers +v0x55cf9dc1c9b0_0 .net "in", 7 0, L_0x55cf9dc4d000; alias, 1 drivers +v0x55cf9dc1ca90_0 .net "load", 0 0, L_0x7fcf8ba88720; alias, 1 drivers +v0x55cf9dc1cb90_0 .var "out", 7 0; +v0x55cf9dc1cc60_0 .var "reset", 0 0; +v0x55cf9dc1cd50_0 .net "rst", 0 0, v0x55cf9dc32230_0; alias, 1 drivers +v0x55cf9dc1cdf0_0 .net "save", 0 0, L_0x55cf9dc4d1d0; alias, 1 drivers +v0x55cf9dc1ce90_0 .var "value", 7 0; +E_0x55cf9dc1c890/0 .event negedge, v0x55cf9dc1b8f0_0; +E_0x55cf9dc1c890/1 .event posedge, v0x55cf9dc1b8f0_0; +E_0x55cf9dc1c890 .event/or E_0x55cf9dc1c890/0, E_0x55cf9dc1c890/1; +S_0x55cf9dc1db70 .scope module, "RegisterPlus_55" "RegisterPlus" 3 67, 35 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "Load"; + .port_info 3 /INPUT 8 "Save_value"; + .port_info 4 /INPUT 1 "Save"; + .port_info 5 /OUTPUT 8 "Always_output"; + .port_info 6 /OUTPUT 8 "Output"; +P_0x55cf9dc1dd50 .param/str "NAME" 0 35 3, "\000"; +P_0x55cf9dc1dd90 .param/l "UUID" 0 35 2, C4<0011111010111000010000010110101110101111010111110111101101010010>; +L_0x55cf9dc4d320 .functor BUFZ 8, L_0x55cf9dc50da0, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x55cf9dc4d3d0 .functor BUFZ 1, v0x55cf9dc09b10_0, C4<0>, C4<0>, C4<0>; +L_0x55cf9dc4d4b0 .functor BUFZ 8, v0x55cf9dc1f7b0_0, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x55cf9dc4d5d0 .functor BUFZ 1, v0x55cf9dc0ab40_0, C4<0>, C4<0>, C4<0>; +v0x55cf9dc1fc90_0 .net "Always_output", 7 0, L_0x55cf9dc4d4b0; alias, 1 drivers +v0x55cf9dc1fd70_0 .net "Load", 0 0, v0x55cf9dc09b10_0; alias, 1 drivers +v0x55cf9dc1fe40_0 .net "Output", 7 0, v0x55cf9dc1ee00_0; alias, 1 drivers +v0x55cf9dc1ff40_0 .net "Save", 0 0, v0x55cf9dc0ab40_0; alias, 1 drivers +v0x55cf9dc20010_0 .net "Save_value", 7 0, L_0x55cf9dc50da0; alias, 1 drivers +v0x55cf9dc20190_0 .net "clk", 0 0, v0x55cf9dc31950_0; alias, 1 drivers +v0x55cf9dc20440_0 .net "rst", 0 0, v0x55cf9dc32230_0; alias, 1 drivers +v0x55cf9dc206f0_0 .net "wire_0", 7 0, L_0x55cf9dc4d320; 1 drivers +v0x55cf9dc20790_0 .net "wire_1", 0 0, L_0x55cf9dc4d3d0; 1 drivers +L_0x7fcf8ba88768 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +v0x55cf9dc208f0_0 .net "wire_2", 0 0, L_0x7fcf8ba88768; 1 drivers +v0x55cf9dc20990_0 .net "wire_3", 7 0, v0x55cf9dc1f7b0_0; 1 drivers +v0x55cf9dc20a50_0 .net "wire_4", 0 0, L_0x55cf9dc4d5d0; 1 drivers +S_0x55cf9dc1dfa0 .scope module, "On_1" "TC_Constant" 35 14, 8 2 0, S_0x55cf9dc1db70; + .timescale -8 -9; + .port_info 0 /OUTPUT 1 "out"; +P_0x55cf9dc1b5d0 .param/l "BIT_WIDTH" 0 8 5, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dc1b610 .param/str "NAME" 0 8 4, "\000"; +P_0x55cf9dc1b650 .param/l "UUID" 0 8 3, C4<0011111010111000010000010110101110101111010111110111101101010000>; +P_0x55cf9dc1b690 .param/l "value" 0 8 6, C4<1>; +v0x55cf9dc1e510_0 .net "out", 0 0, L_0x7fcf8ba88768; alias, 1 drivers +S_0x55cf9dc1e650 .scope module, "Output8z_2" "TC_Switch" 35 15, 16 1 0, S_0x55cf9dc1db70; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dc1e830 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dc1e870 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dc1e8b0 .param/l "UUID" 0 16 2, C4<0000111101110001000101011110010110000001100100010101100100011100>; +v0x55cf9dc1eb80_0 .net "en", 0 0, L_0x55cf9dc4d3d0; alias, 1 drivers +v0x55cf9dc1ec60_0 .net "in", 7 0, v0x55cf9dc1f7b0_0; alias, 1 drivers +v0x55cf9dc1ed40_0 .net "out", 7 0, v0x55cf9dc1ee00_0; alias, 1 drivers +v0x55cf9dc1ee00_0 .var "outval", 7 0; +E_0x55cf9dc1eb00 .event anyedge, v0x55cf9dc1ec60_0, v0x55cf9dc1eb80_0; +S_0x55cf9dc1ef60 .scope module, "Register8_0" "TC_Register" 35 13, 36 1 0, S_0x55cf9dc1db70; + .timescale -8 -9; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "load"; + .port_info 3 /INPUT 1 "save"; + .port_info 4 /INPUT 8 "in"; + .port_info 5 /OUTPUT 8 "out"; +P_0x55cf9dc1f170 .param/l "BIT_WIDTH" 0 36 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dc1f1b0 .param/str "NAME" 0 36 3, "\000"; +P_0x55cf9dc1f1f0 .param/l "UUID" 0 36 2, C4<0011111010111000010000010110101110101111010111110111101101010011>; +v0x55cf9dc1f510_0 .net "clk", 0 0, v0x55cf9dc31950_0; alias, 1 drivers +v0x55cf9dc1f5d0_0 .net "in", 7 0, L_0x55cf9dc4d320; alias, 1 drivers +v0x55cf9dc1f6b0_0 .net "load", 0 0, L_0x7fcf8ba88768; alias, 1 drivers +v0x55cf9dc1f7b0_0 .var "out", 7 0; +v0x55cf9dc1f880_0 .var "reset", 0 0; +v0x55cf9dc1f970_0 .net "rst", 0 0, v0x55cf9dc32230_0; alias, 1 drivers +v0x55cf9dc1fa10_0 .net "save", 0 0, L_0x55cf9dc4d5d0; alias, 1 drivers +v0x55cf9dc1fab0_0 .var "value", 7 0; +E_0x55cf9dc1f4b0/0 .event negedge, v0x55cf9dc1e510_0; +E_0x55cf9dc1f4b0/1 .event posedge, v0x55cf9dc1e510_0; +E_0x55cf9dc1f4b0 .event/or E_0x55cf9dc1f4b0/0, E_0x55cf9dc1f4b0/1; +S_0x55cf9dc20bd0 .scope module, "RegisterPlus_56" "RegisterPlus" 3 68, 35 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "Load"; + .port_info 3 /INPUT 8 "Save_value"; + .port_info 4 /INPUT 1 "Save"; + .port_info 5 /OUTPUT 8 "Always_output"; + .port_info 6 /OUTPUT 8 "Output"; +P_0x55cf9dc20db0 .param/str "NAME" 0 35 3, "\000"; +P_0x55cf9dc20df0 .param/l "UUID" 0 35 2, C4<0011010110001001101000101110011010111101110101110001111111001111>; +L_0x55cf9dc4d6d0 .functor BUFZ 8, L_0x55cf9dc50da0, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x55cf9dc4d7d0 .functor BUFZ 1, v0x55cf9dc09bd0_0, C4<0>, C4<0>, C4<0>; +L_0x55cf9dc4d8b0 .functor BUFZ 8, v0x55cf9dc22700_0, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x55cf9dc4d9d0 .functor BUFZ 1, v0x55cf9dc0ac00_0, C4<0>, C4<0>, C4<0>; +v0x55cf9dc22be0_0 .net "Always_output", 7 0, L_0x55cf9dc4d8b0; alias, 1 drivers +v0x55cf9dc22cc0_0 .net "Load", 0 0, v0x55cf9dc09bd0_0; alias, 1 drivers +v0x55cf9dc22d90_0 .net "Output", 7 0, v0x55cf9dc21d50_0; alias, 1 drivers +v0x55cf9dc22e90_0 .net "Save", 0 0, v0x55cf9dc0ac00_0; alias, 1 drivers +v0x55cf9dc22f60_0 .net "Save_value", 7 0, L_0x55cf9dc50da0; alias, 1 drivers +v0x55cf9dc23050_0 .net "clk", 0 0, v0x55cf9dc31950_0; alias, 1 drivers +v0x55cf9dc230f0_0 .net "rst", 0 0, v0x55cf9dc32230_0; alias, 1 drivers +v0x55cf9dc23190_0 .net "wire_0", 7 0, L_0x55cf9dc4d6d0; 1 drivers +v0x55cf9dc23230_0 .net "wire_1", 0 0, L_0x55cf9dc4d7d0; 1 drivers +L_0x7fcf8ba887b0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +v0x55cf9dc23390_0 .net "wire_2", 0 0, L_0x7fcf8ba887b0; 1 drivers +v0x55cf9dc23430_0 .net "wire_3", 7 0, v0x55cf9dc22700_0; 1 drivers +v0x55cf9dc23540_0 .net "wire_4", 0 0, L_0x55cf9dc4d9d0; 1 drivers +S_0x55cf9dc21000 .scope module, "On_1" "TC_Constant" 35 14, 8 2 0, S_0x55cf9dc20bd0; + .timescale -8 -9; + .port_info 0 /OUTPUT 1 "out"; +P_0x55cf9dc150b0 .param/l "BIT_WIDTH" 0 8 5, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dc150f0 .param/str "NAME" 0 8 4, "\000"; +P_0x55cf9dc15130 .param/l "UUID" 0 8 3, C4<0011010110001001101000101110011010111101110101110001111111001101>; +P_0x55cf9dc15170 .param/l "value" 0 8 6, C4<1>; +v0x55cf9dc21460_0 .net "out", 0 0, L_0x7fcf8ba887b0; alias, 1 drivers +S_0x55cf9dc215a0 .scope module, "Output8z_2" "TC_Switch" 35 15, 16 1 0, S_0x55cf9dc20bd0; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dc21780 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dc217c0 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dc21800 .param/l "UUID" 0 16 2, C4<0000010001000000111101100110100010010011000110010011110110000001>; +v0x55cf9dc21ad0_0 .net "en", 0 0, L_0x55cf9dc4d7d0; alias, 1 drivers +v0x55cf9dc21bb0_0 .net "in", 7 0, v0x55cf9dc22700_0; alias, 1 drivers +v0x55cf9dc21c90_0 .net "out", 7 0, v0x55cf9dc21d50_0; alias, 1 drivers +v0x55cf9dc21d50_0 .var "outval", 7 0; +E_0x55cf9dc21a50 .event anyedge, v0x55cf9dc21bb0_0, v0x55cf9dc21ad0_0; +S_0x55cf9dc21eb0 .scope module, "Register8_0" "TC_Register" 35 13, 36 1 0, S_0x55cf9dc20bd0; + .timescale -8 -9; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "load"; + .port_info 3 /INPUT 1 "save"; + .port_info 4 /INPUT 8 "in"; + .port_info 5 /OUTPUT 8 "out"; +P_0x55cf9dc220c0 .param/l "BIT_WIDTH" 0 36 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dc22100 .param/str "NAME" 0 36 3, "\000"; +P_0x55cf9dc22140 .param/l "UUID" 0 36 2, C4<0011010110001001101000101110011010111101110101110001111111001110>; +v0x55cf9dc22460_0 .net "clk", 0 0, v0x55cf9dc31950_0; alias, 1 drivers +v0x55cf9dc22520_0 .net "in", 7 0, L_0x55cf9dc4d6d0; alias, 1 drivers +v0x55cf9dc22600_0 .net "load", 0 0, L_0x7fcf8ba887b0; alias, 1 drivers +v0x55cf9dc22700_0 .var "out", 7 0; +v0x55cf9dc227d0_0 .var "reset", 0 0; +v0x55cf9dc228c0_0 .net "rst", 0 0, v0x55cf9dc32230_0; alias, 1 drivers +v0x55cf9dc22960_0 .net "save", 0 0, L_0x55cf9dc4d9d0; alias, 1 drivers +v0x55cf9dc22a00_0 .var "value", 7 0; +E_0x55cf9dc22400/0 .event negedge, v0x55cf9dc21460_0; +E_0x55cf9dc22400/1 .event posedge, v0x55cf9dc21460_0; +E_0x55cf9dc22400 .event/or E_0x55cf9dc22400/0, E_0x55cf9dc22400/1; +S_0x55cf9dc236c0 .scope module, "Splitter16_38" "TC_Splitter16" 3 50, 37 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 16 "in"; + .port_info 1 /OUTPUT 8 "out0"; + .port_info 2 /OUTPUT 8 "out1"; +P_0x55cf9dc238a0 .param/str "NAME" 0 37 3, "\000"; +P_0x55cf9dc238e0 .param/l "UUID" 0 37 2, C4<0010011100011000100011100100101100101000101110111011100100110011>; +L_0x55cf9dc4b4a0 .functor BUFZ 16, L_0x55cf9dc4c240, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +v0x55cf9dc23ab0_0 .net *"_ivl_4", 15 0, L_0x55cf9dc4b4a0; 1 drivers +v0x55cf9dc23bb0_0 .net "in", 15 0, L_0x55cf9dc4c240; alias, 1 drivers +v0x55cf9dc23c70_0 .net "out0", 7 0, L_0x55cf9dc4b400; alias, 1 drivers +v0x55cf9dc23d40_0 .net "out1", 7 0, L_0x55cf9dc4b360; alias, 1 drivers +L_0x55cf9dc4b360 .part L_0x55cf9dc4b4a0, 8, 8; +L_0x55cf9dc4b400 .part L_0x55cf9dc4b4a0, 0, 8; +S_0x55cf9dc23ea0 .scope module, "Splitter16_44" "TC_Splitter16" 3 56, 37 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 16 "in"; + .port_info 1 /OUTPUT 8 "out0"; + .port_info 2 /OUTPUT 8 "out1"; +P_0x55cf9dc24080 .param/str "NAME" 0 37 3, "\000"; +P_0x55cf9dc240c0 .param/l "UUID" 0 37 2, C4<0011110010010001111100000001110100011000101001101010001010100111>; +L_0x55cf9dc4bae0 .functor BUFZ 16, v0x55cf9dc25be0_0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +v0x55cf9dc24270_0 .net *"_ivl_4", 15 0, L_0x55cf9dc4bae0; 1 drivers +v0x55cf9dc24370_0 .net "in", 15 0, v0x55cf9dc25be0_0; alias, 1 drivers +v0x55cf9dc24450_0 .net "out0", 7 0, L_0x55cf9dc4ba40; alias, 1 drivers +v0x55cf9dc24550_0 .net "out1", 7 0, L_0x55cf9dc4b9a0; alias, 1 drivers +L_0x55cf9dc4b9a0 .part L_0x55cf9dc4bae0, 8, 8; +L_0x55cf9dc4ba40 .part L_0x55cf9dc4bae0, 0, 8; +S_0x55cf9dc24680 .scope module, "Splitter8_19" "TC_Splitter8" 3 31, 21 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 8 "in"; + .port_info 1 /OUTPUT 1 "out0"; + .port_info 2 /OUTPUT 1 "out1"; + .port_info 3 /OUTPUT 1 "out2"; + .port_info 4 /OUTPUT 1 "out3"; + .port_info 5 /OUTPUT 1 "out4"; + .port_info 6 /OUTPUT 1 "out5"; + .port_info 7 /OUTPUT 1 "out6"; + .port_info 8 /OUTPUT 1 "out7"; +P_0x55cf9dc24860 .param/str "NAME" 0 21 3, "\000"; +P_0x55cf9dc248a0 .param/l "UUID" 0 21 2, C4<0000001111001110110110001011101001100101010111100101000100110011>; +L_0x55cf9dc4a230 .functor BUFZ 8, L_0x55cf9dc49410, C4<00000000>, C4<00000000>, C4<00000000>; +v0x55cf9dc24b10_0 .net *"_ivl_10", 7 0, L_0x55cf9dc4a230; 1 drivers +v0x55cf9dc24c10_0 .net "in", 7 0, L_0x55cf9dc49410; alias, 1 drivers +v0x55cf9dc24d20_0 .net "out0", 0 0, L_0x55cf9dc4a140; alias, 1 drivers +v0x55cf9dc24df0_0 .net "out1", 0 0, L_0x55cf9dc4a0a0; alias, 1 drivers +v0x55cf9dc24ec0_0 .net "out2", 0 0, L_0x55cf9dc49fc0; alias, 1 drivers +v0x55cf9dc24fb0_0 .net "out3", 0 0, L_0x55cf9dc49f20; alias, 1 drivers +v0x55cf9dc25080_0 .net "out4", 0 0, L_0x55cf9dc49dc0; alias, 1 drivers +v0x55cf9dc25150_0 .net "out5", 0 0, L_0x55cf9dc49d20; alias, 1 drivers +v0x55cf9dc25220_0 .net "out6", 0 0, L_0x55cf9dc49c80; 1 drivers +v0x55cf9dc25350_0 .net "out7", 0 0, L_0x55cf9dc48d00; 1 drivers +L_0x55cf9dc48d00 .part L_0x55cf9dc4a230, 7, 1; +L_0x55cf9dc49c80 .part L_0x55cf9dc4a230, 6, 1; +L_0x55cf9dc49d20 .part L_0x55cf9dc4a230, 5, 1; +L_0x55cf9dc49dc0 .part L_0x55cf9dc4a230, 4, 1; +L_0x55cf9dc49f20 .part L_0x55cf9dc4a230, 3, 1; +L_0x55cf9dc49fc0 .part L_0x55cf9dc4a230, 2, 1; +L_0x55cf9dc4a0a0 .part L_0x55cf9dc4a230, 1, 1; +L_0x55cf9dc4a140 .part L_0x55cf9dc4a230, 0, 1; +S_0x55cf9dc25470 .scope module, "Switch16_47" "TC_Switch" 3 59, 16 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 16 "in"; + .port_info 2 /OUTPUT 16 "out"; +P_0x55cf9dc25600 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000010000>; +P_0x55cf9dc25640 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dc25680 .param/l "UUID" 0 16 2, C4<0001110100101101100100111100101000101011111111010111110001011000>; +v0x55cf9dc25930_0 .net "en", 0 0, L_0x55cf9dc4e430; alias, 1 drivers +v0x55cf9dc259f0_0 .net "in", 15 0, L_0x55cf9dc4a2a0; alias, 1 drivers +v0x55cf9dc25ae0_0 .net "out", 15 0, v0x55cf9dc25be0_0; alias, 1 drivers +v0x55cf9dc25be0_0 .var "outval", 15 0; +E_0x55cf9dc12d30 .event anyedge, v0x55cf9dc0d240_0, v0x55cf9dbf4960_0; +S_0x55cf9dc25d00 .scope module, "Switch8_0" "TC_Switch" 3 12, 16 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dc25ee0 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dc25f20 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dc25f60 .param/l "UUID" 0 16 2, C4<0001011111001111011111001100000101010011101101100001100111110010>; +v0x55cf9dc26230_0 .net "en", 0 0, L_0x55cf9dc4a530; alias, 1 drivers +v0x55cf9dc26320_0 .net "in", 7 0, v0x55cf9dc11140_0; alias, 1 drivers +v0x55cf9dc26410_0 .net "out", 7 0, v0x55cf9dc264e0_0; alias, 1 drivers +v0x55cf9dc264e0_0 .var "outval", 7 0; +E_0x55cf9dc261b0 .event anyedge, v0x55cf9dbfbd30_0, v0x55cf9dbf4a60_0; +S_0x55cf9dc26620 .scope module, "Switch8_22" "TC_Switch" 3 34, 16 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dc26800 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dc26840 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dc26880 .param/l "UUID" 0 16 2, C4<0011110110110001010010110110011011110100010110100011111010000101>; +v0x55cf9dc26b50_0 .net "en", 0 0, v0x55cf9dc09c90_0; alias, 1 drivers +v0x55cf9dc26c10_0 .net "in", 7 0, L_0x55cf9dc49b40; alias, 1 drivers +v0x55cf9dc26d00_0 .net "out", 7 0, v0x55cf9dc26dd0_0; alias, 1 drivers +v0x55cf9dc26dd0_0 .var "outval", 7 0; +E_0x55cf9dc26ad0 .event anyedge, v0x55cf9dbf9580_0, v0x55cf9dbf64b0_0; +S_0x55cf9dc26f30 .scope module, "Switch8_23" "TC_Switch" 3 35, 16 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dc27110 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dc27150 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dc27190 .param/l "UUID" 0 16 2, C4<0000011110111001111001111010011000000000111100001111110000001000>; +v0x55cf9dc27460_0 .net "en", 0 0, v0x55cf9dc0acc0_0; alias, 1 drivers +v0x55cf9dc27520_0 .net "in", 7 0, L_0x55cf9dc512e0; alias, 1 drivers +v0x55cf9dc27600_0 .net "out", 7 0, v0x55cf9dc27700_0; alias, 1 drivers +v0x55cf9dc27700_0 .var "outval", 7 0; +E_0x55cf9dc273e0 .event anyedge, v0x55cf9dc27520_0, v0x55cf9dbf5dd0_0; +S_0x55cf9dc27840 .scope module, "Switch8_25" "TC_Switch" 3 37, 16 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dc27a20 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dc27a60 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dc27aa0 .param/l "UUID" 0 16 2, C4<0001100111010001010001001010110111110110100110100001001110011101>; +v0x55cf9dc27d70_0 .net "en", 0 0, L_0x55cf9dc4b860; alias, 1 drivers +v0x55cf9dc27e60_0 .net "in", 7 0, L_0x55cf9dc512e0; alias, 1 drivers +v0x55cf9dc27f30_0 .net "out", 7 0, v0x55cf9dc28000_0; alias, 1 drivers +v0x55cf9dc28000_0 .var "outval", 7 0; +E_0x55cf9dc27cf0 .event anyedge, v0x55cf9dc27520_0, v0x55cf9dbf4380_0; +S_0x55cf9dc28160 .scope module, "Switch8_29" "TC_Switch" 3 41, 16 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dc28340 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dc28380 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dc283c0 .param/l "UUID" 0 16 2, C4<0001000101010001101101100111010100110010100101111100111110011000>; +v0x55cf9dc28690_0 .net "en", 0 0, L_0x55cf9dc4e350; alias, 1 drivers +v0x55cf9dc28750_0 .net "in", 7 0, L_0x55cf9dc49410; alias, 1 drivers +v0x55cf9dc28810_0 .net "out", 7 0, v0x55cf9dc28900_0; alias, 1 drivers +v0x55cf9dc28900_0 .var "outval", 7 0; +E_0x55cf9dc28610 .event anyedge, v0x55cf9dbfbe30_0, v0x55cf9dc088c0_0; +S_0x55cf9dc28a60 .scope module, "Switch8_31" "TC_Switch" 3 43, 16 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dc28c40 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dc28c80 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dc28cc0 .param/l "UUID" 0 16 2, C4<0010100000100110101100000000001000111011001100011101101101101010>; +v0x55cf9dc28f90_0 .net "en", 0 0, L_0x55cf9dc4e430; alias, 1 drivers +v0x55cf9dc290e0_0 .net "in", 7 0, L_0x55cf9dc4b400; alias, 1 drivers +v0x55cf9dc291d0_0 .net "out", 7 0, v0x55cf9dc292a0_0; alias, 1 drivers +v0x55cf9dc292a0_0 .var "outval", 7 0; +E_0x55cf9dc28f10 .event anyedge, v0x55cf9dc23c70_0, v0x55cf9dbf4960_0; +S_0x55cf9dc29400 .scope module, "Switch8_33" "TC_Switch" 3 45, 16 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dc29590 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dc295d0 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dc29610 .param/l "UUID" 0 16 2, C4<0000110011100100101111111110100000100110101101010010011110111101>; +v0x55cf9dc298e0_0 .net "en", 0 0, L_0x55cf9dc4e250; alias, 1 drivers +v0x55cf9dc29a30_0 .net "in", 7 0, L_0x55cf9dc49410; alias, 1 drivers +v0x55cf9dc29b80_0 .net "out", 7 0, v0x55cf9dc29c80_0; alias, 1 drivers +v0x55cf9dc29c80_0 .var "outval", 7 0; +E_0x55cf9dc29860 .event anyedge, v0x55cf9dbfbe30_0, v0x55cf9dbf3bd0_0; +S_0x55cf9dc29dc0 .scope module, "Switch8_39" "TC_Switch" 3 51, 16 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "en"; + .port_info 1 /INPUT 8 "in"; + .port_info 2 /OUTPUT 8 "out"; +P_0x55cf9dc29f50 .param/l "BIT_WIDTH" 0 16 4, C4<0000000000000000000000000000000000000000000000000000000000001000>; +P_0x55cf9dc29f90 .param/str "NAME" 0 16 3, "\000"; +P_0x55cf9dc29fd0 .param/l "UUID" 0 16 2, C4<0001111100111110011011001100000110110011110110011101000001101101>; +v0x55cf9dc2a250_0 .net "en", 0 0, L_0x55cf9dc4b220; alias, 1 drivers +v0x55cf9dc2a340_0 .net "in", 7 0, L_0x55cf9dc4b360; alias, 1 drivers +v0x55cf9dc2a410_0 .net "out", 7 0, v0x55cf9dc2a4e0_0; alias, 1 drivers +v0x55cf9dc2a4e0_0 .var "outval", 7 0; +E_0x55cf9dc2a1d0 .event anyedge, v0x55cf9dc23d40_0, v0x55cf9dbf5810_0; +S_0x55cf9dc2a640 .scope module, "Xor_21" "TC_Xor" 3 33, 23 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "in0"; + .port_info 1 /INPUT 1 "in1"; + .port_info 2 /OUTPUT 1 "out"; +P_0x55cf9dc2a820 .param/l "BIT_WIDTH" 0 23 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dc2a860 .param/str "NAME" 0 23 3, "\000"; +P_0x55cf9dc2a8a0 .param/l "UUID" 0 23 2, C4<0011011110111000100011111111111010011110111000010101110010100000>; +L_0x55cf9dc4a360 .functor XOR 1, L_0x55cf9dc4a670, v0x55cf9dc0a800_0, C4<0>, C4<0>; +v0x55cf9dc2aaf0_0 .net "in0", 0 0, L_0x55cf9dc4a670; alias, 1 drivers +v0x55cf9dc2ac00_0 .net "in1", 0 0, v0x55cf9dc0a800_0; alias, 1 drivers +v0x55cf9dc2acd0_0 .net "out", 0 0, L_0x55cf9dc4a360; alias, 1 drivers +S_0x55cf9dc2ae10 .scope module, "Xor_27" "TC_Xor" 3 39, 23 1 0, S_0x55cf9dbb0f60; + .timescale -8 -9; + .port_info 0 /INPUT 1 "in0"; + .port_info 1 /INPUT 1 "in1"; + .port_info 2 /OUTPUT 1 "out"; +P_0x55cf9dc2aff0 .param/l "BIT_WIDTH" 0 23 4, C4<0000000000000000000000000000000000000000000000000000000000000001>; +P_0x55cf9dc2b030 .param/str "NAME" 0 23 3, "\000"; +P_0x55cf9dc2b070 .param/l "UUID" 0 23 2, C4<0001010100010001010010001101110110101010111111110011110010100001>; +L_0x55cf9dc4a7b0 .functor XOR 1, v0x55cf9dc0aa30_0, L_0x55cf9dc4e430, C4<0>, C4<0>; +v0x55cf9dc2b2c0_0 .net "in0", 0 0, v0x55cf9dc0aa30_0; alias, 1 drivers +v0x55cf9dc2b3d0_0 .net "in1", 0 0, L_0x55cf9dc4e430; alias, 1 drivers +v0x55cf9dc2b470_0 .net "out", 0 0, L_0x55cf9dc4a7b0; alias, 1 drivers + .scope S_0x55cf9dc25d00; +T_0 ; + %wait E_0x55cf9dc261b0; + %load/vec4 v0x55cf9dc26230_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_0.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_0.1, 6; + %jmp T_0.2; +T_0.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc264e0_0, 0, 8; + %jmp T_0.2; +T_0.1 ; + %load/vec4 v0x55cf9dc26320_0; + %store/vec4 v0x55cf9dc264e0_0, 0, 8; + %jmp T_0.2; +T_0.2 ; + %pop/vec4 1; + %jmp T_0; + .thread T_0, $push; + .scope S_0x55cf9dc0b250; +T_1 ; + %wait E_0x55cf9dc0b6a0; + %load/vec4 v0x55cf9dc0b870_0; + %flag_set/vec4 8; + %jmp/0xz T_1.0, 8; + %vpi_call 29 11 "$display", "%s", P_0x55cf9dc0b3e0 {0 0 0}; + %vpi_call 29 12 "$stop" {0 0 0}; +T_1.0 ; + %jmp T_1; + .thread T_1; + .scope S_0x55cf9dc0c370; +T_2 ; + %wait E_0x55cf9dc0c820; + %load/vec4 v0x55cf9dc0c8a0_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_2.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_2.1, 6; + %jmp T_2.2; +T_2.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc0cb30_0, 0, 8; + %jmp T_2.2; +T_2.1 ; + %load/vec4 v0x55cf9dc0c990_0; + %store/vec4 v0x55cf9dc0cb30_0, 0, 8; + %jmp T_2.2; +T_2.2 ; + %pop/vec4 1; + %jmp T_2; + .thread T_2, $push; + .scope S_0x55cf9dc10510; +T_3 ; + %pushi/vec4 3739936992, 0, 8098; + %concati/vec4 3739543742, 0, 32; + %concati/vec4 3905611496, 0, 32; + %concati/vec4 778201454, 0, 31; + %store/vec4 v0x55cf9dc10e70_0, 0, 8193; + %vpi_call 33 21 "$display", "param %0s", v0x55cf9dc10e70_0 {0 0 0}; + %vpi_func 33 22 "$value$plusargs" 32, P_0x55cf9dc106f0, v0x55cf9dc10e70_0 {0 0 0}; + %store/vec4 v0x55cf9dc10f50_0, 0, 32; + %vpi_call 33 23 "$display", "loading %0s", v0x55cf9dc10e70_0 {0 0 0}; + %vpi_func 33 24 "$fopen" 32, v0x55cf9dc10e70_0, "r" {0 0 0}; + %store/vec4 v0x55cf9dc10dd0_0, 0, 32; + %load/vec4 v0x55cf9dc10dd0_0; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_3.0, 4; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x55cf9dc10f50_0, 0, 32; +T_3.2 ; + %vpi_func 33 27 "$feof" 32, v0x55cf9dc10dd0_0 {0 0 0}; + %nor/r; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_3.4, 9; + %load/vec4 v0x55cf9dc10f50_0; + %cmpi/s 256, 0, 32; + %flag_get/vec4 5; + %and; +T_3.4; + %flag_set/vec4 8; + %jmp/0xz T_3.3, 8; + %vpi_func 33 28 "$fgetc" 32, v0x55cf9dc10dd0_0 {0 0 0}; + %pad/s 8; + %ix/getv/s 4, v0x55cf9dc10f50_0; + %store/vec4a v0x55cf9dc11080, 4, 0; + %load/vec4 v0x55cf9dc10f50_0; + %addi 1, 0, 32; + %store/vec4 v0x55cf9dc10f50_0, 0, 32; + %jmp T_3.2; +T_3.3 ; + %vpi_call 33 31 "$display", "read %0d bytes", v0x55cf9dc10f50_0 {0 0 0}; + %jmp T_3.1; +T_3.0 ; + %vpi_call 33 33 "$display", "file not found" {0 0 0}; +T_3.1 ; + %vpi_call 33 35 "$fclose", v0x55cf9dc10dd0_0 {0 0 0}; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc11140_0, 0, 8; + %end; + .thread T_3; + .scope S_0x55cf9dc10510; +T_4 ; + %wait E_0x55cf9dc10b60; + %load/vec4 v0x55cf9dc11200_0; + %flag_set/vec4 8; + %jmp/0xz T_4.0, 8; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc11140_0, 0, 8; + %jmp T_4.1; +T_4.0 ; + %load/vec4 v0x55cf9dc10be0_0; + %pad/u 10; + %ix/vec4 4; + %load/vec4a v0x55cf9dc11080, 4; + %store/vec4 v0x55cf9dc11140_0, 0, 8; +T_4.1 ; + %jmp T_4; + .thread T_4, $push; + .scope S_0x55cf9dc0baf0; +T_5 ; + %wait E_0x55cf9dc0bf00; + %load/vec4 v0x55cf9dc0bf80_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_5.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_5.1, 6; + %jmp T_5.2; +T_5.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc0c230_0, 0, 8; + %jmp T_5.2; +T_5.1 ; + %load/vec4 v0x55cf9dc0c070_0; + %store/vec4 v0x55cf9dc0c230_0, 0, 8; + %jmp T_5.2; +T_5.2 ; + %pop/vec4 1; + %jmp T_5; + .thread T_5, $push; + .scope S_0x55cf9db900c0; +T_6 ; + %wait E_0x55cf9d9d07d0; + %load/vec4 v0x55cf9db8af80_0; + %load/vec4 v0x55cf9db7ef90_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55cf9db7fc70_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55cf9db80950_0; + %concat/vec4; draw_concat_vec4 + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_6.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_6.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_6.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_6.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_6.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_6.5, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_6.6, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_6.7, 6; + %pushi/vec4 0, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9db52ea0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db89ee0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db87f80_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db87240_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db86500_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db83080_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db82370_0, 0, 1; + %store/vec4 v0x55cf9db81660_0, 0, 1; + %jmp T_6.9; +T_6.0 ; + %pushi/vec4 1, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9db52ea0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db89ee0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db87f80_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db87240_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db86500_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db83080_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db82370_0, 0, 1; + %store/vec4 v0x55cf9db81660_0, 0, 1; + %jmp T_6.9; +T_6.1 ; + %pushi/vec4 2, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9db52ea0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db89ee0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db87f80_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db87240_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db86500_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db83080_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db82370_0, 0, 1; + %store/vec4 v0x55cf9db81660_0, 0, 1; + %jmp T_6.9; +T_6.2 ; + %pushi/vec4 4, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9db52ea0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db89ee0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db87f80_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db87240_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db86500_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db83080_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db82370_0, 0, 1; + %store/vec4 v0x55cf9db81660_0, 0, 1; + %jmp T_6.9; +T_6.3 ; + %pushi/vec4 8, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9db52ea0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db89ee0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db87f80_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db87240_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db86500_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db83080_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db82370_0, 0, 1; + %store/vec4 v0x55cf9db81660_0, 0, 1; + %jmp T_6.9; +T_6.4 ; + %pushi/vec4 16, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9db52ea0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db89ee0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db87f80_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db87240_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db86500_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db83080_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db82370_0, 0, 1; + %store/vec4 v0x55cf9db81660_0, 0, 1; + %jmp T_6.9; +T_6.5 ; + %pushi/vec4 32, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9db52ea0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db89ee0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db87f80_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db87240_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db86500_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db83080_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db82370_0, 0, 1; + %store/vec4 v0x55cf9db81660_0, 0, 1; + %jmp T_6.9; +T_6.6 ; + %pushi/vec4 64, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9db52ea0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db89ee0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db87f80_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db87240_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db86500_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db83080_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db82370_0, 0, 1; + %store/vec4 v0x55cf9db81660_0, 0, 1; + %jmp T_6.9; +T_6.7 ; + %pushi/vec4 128, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9db52ea0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db89ee0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db87f80_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db87240_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db86500_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db83080_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db82370_0, 0, 1; + %store/vec4 v0x55cf9db81660_0, 0, 1; + %jmp T_6.9; +T_6.9 ; + %pop/vec4 1; + %jmp T_6; + .thread T_6, $push; + .scope S_0x55cf9da255b0; +T_7 ; + %wait E_0x55cf9d95e730; + %load/vec4 v0x55cf9d95e7b0_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_7.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_7.1, 6; + %jmp T_7.2; +T_7.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbd37c0_0, 0, 8; + %jmp T_7.2; +T_7.1 ; + %load/vec4 v0x55cf9d95e8c0_0; + %store/vec4 v0x55cf9dbd37c0_0, 0, 8; + %jmp T_7.2; +T_7.2 ; + %pop/vec4 1; + %jmp T_7; + .thread T_7, $push; + .scope S_0x55cf9dbd4b70; +T_8 ; + %wait E_0x55cf9dbd5020; + %load/vec4 v0x55cf9dbd50a0_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_8.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_8.1, 6; + %jmp T_8.2; +T_8.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbd5320_0, 0, 8; + %jmp T_8.2; +T_8.1 ; + %load/vec4 v0x55cf9dbd5160_0; + %store/vec4 v0x55cf9dbd5320_0, 0, 8; + %jmp T_8.2; +T_8.2 ; + %pop/vec4 1; + %jmp T_8; + .thread T_8, $push; + .scope S_0x55cf9dbdacb0; +T_9 ; + %wait E_0x55cf9dbdb160; + %load/vec4 v0x55cf9dbdb1e0_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_9.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_9.1, 6; + %jmp T_9.2; +T_9.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbdb460_0, 0, 8; + %jmp T_9.2; +T_9.1 ; + %load/vec4 v0x55cf9dbdb2a0_0; + %store/vec4 v0x55cf9dbdb460_0, 0, 8; + %jmp T_9.2; +T_9.2 ; + %pop/vec4 1; + %jmp T_9; + .thread T_9, $push; + .scope S_0x55cf9dbe9290; +T_10 ; + %wait E_0x55cf9da22b30; + %load/vec4 v0x55cf9dbe9740_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_10.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_10.1, 6; + %jmp T_10.2; +T_10.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbe99c0_0, 0, 8; + %jmp T_10.2; +T_10.1 ; + %load/vec4 v0x55cf9dbe9800_0; + %store/vec4 v0x55cf9dbe99c0_0, 0, 8; + %jmp T_10.2; +T_10.2 ; + %pop/vec4 1; + %jmp T_10; + .thread T_10, $push; + .scope S_0x55cf9dbe9b00; +T_11 ; + %wait E_0x55cf9d94e780; + %load/vec4 v0x55cf9dbe9fb0_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_11.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_11.1, 6; + %jmp T_11.2; +T_11.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbea230_0, 0, 8; + %jmp T_11.2; +T_11.1 ; + %load/vec4 v0x55cf9dbea070_0; + %store/vec4 v0x55cf9dbea230_0, 0, 8; + %jmp T_11.2; +T_11.2 ; + %pop/vec4 1; + %jmp T_11; + .thread T_11, $push; + .scope S_0x55cf9da42e60; +T_12 ; + %wait E_0x55cf9da432a0; + %load/vec4 v0x55cf9da214b0_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_12.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_12.1, 6; + %jmp T_12.2; +T_12.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9da75b60_0, 0, 8; + %jmp T_12.2; +T_12.1 ; + %load/vec4 v0x55cf9da759d0_0; + %store/vec4 v0x55cf9da75b60_0, 0, 8; + %jmp T_12.2; +T_12.2 ; + %pop/vec4 1; + %jmp T_12; + .thread T_12, $push; + .scope S_0x55cf9da75cc0; +T_13 ; + %wait E_0x55cf9da05040; + %load/vec4 v0x55cf9da050c0_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_13.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_13.1, 6; + %jmp T_13.2; +T_13.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9d9a4010_0, 0, 8; + %jmp T_13.2; +T_13.1 ; + %load/vec4 v0x55cf9d9a3e50_0; + %store/vec4 v0x55cf9d9a4010_0, 0, 8; + %jmp T_13.2; +T_13.2 ; + %pop/vec4 1; + %jmp T_13; + .thread T_13, $push; + .scope S_0x55cf9d9a8f20; +T_14 ; + %wait E_0x55cf9d9a9360; + %load/vec4 v0x55cf9d9a4150_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_14.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_14.1, 6; + %jmp T_14.2; +T_14.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9da1fe30_0, 0, 8; + %jmp T_14.2; +T_14.1 ; + %load/vec4 v0x55cf9da1fc80_0; + %store/vec4 v0x55cf9da1fe30_0, 0, 8; + %jmp T_14.2; +T_14.2 ; + %pop/vec4 1; + %jmp T_14; + .thread T_14, $push; + .scope S_0x55cf9da1ff70; +T_15 ; + %wait E_0x55cf9d9759e0; + %load/vec4 v0x55cf9d975a60_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_15.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_15.1, 6; + %jmp T_15.2; +T_15.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9d94b6c0_0, 0, 8; + %jmp T_15.2; +T_15.1 ; + %load/vec4 v0x55cf9d94b500_0; + %store/vec4 v0x55cf9d94b6c0_0, 0, 8; + %jmp T_15.2; +T_15.2 ; + %pop/vec4 1; + %jmp T_15; + .thread T_15, $push; + .scope S_0x55cf9d96e360; +T_16 ; + %wait E_0x55cf9da27240; + %load/vec4 v0x55cf9d94b820_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_16.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_16.1, 6; + %jmp T_16.2; +T_16.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9d9a6e90_0, 0, 8; + %jmp T_16.2; +T_16.1 ; + %load/vec4 v0x55cf9d9a6d30_0; + %store/vec4 v0x55cf9d9a6e90_0, 0, 8; + %jmp T_16.2; +T_16.2 ; + %pop/vec4 1; + %jmp T_16; + .thread T_16, $push; + .scope S_0x55cf9d9a6fb0; +T_17 ; + %wait E_0x55cf9d971000; + %load/vec4 v0x55cf9d971080_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_17.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_17.1, 6; + %jmp T_17.2; +T_17.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9da38680_0, 0, 8; + %jmp T_17.2; +T_17.1 ; + %load/vec4 v0x55cf9da38490_0; + %store/vec4 v0x55cf9da38680_0, 0, 8; + %jmp T_17.2; +T_17.2 ; + %pop/vec4 1; + %jmp T_17; + .thread T_17, $push; + .scope S_0x55cf9d9aabb0; +T_18 ; + %wait E_0x55cf9d971140; + %load/vec4 v0x55cf9da387a0_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_18.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_18.1, 6; + %jmp T_18.2; +T_18.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9da209f0_0, 0, 8; + %jmp T_18.2; +T_18.1 ; + %load/vec4 v0x55cf9da38860_0; + %store/vec4 v0x55cf9da209f0_0, 0, 8; + %jmp T_18.2; +T_18.2 ; + %pop/vec4 1; + %jmp T_18; + .thread T_18, $push; + .scope S_0x55cf9da20b50; +T_19 ; + %wait E_0x55cf9da63b20; + %load/vec4 v0x55cf9da20ce0_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_19.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_19.1, 6; + %jmp T_19.2; +T_19.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9da2bb00_0, 0, 8; + %jmp T_19.2; +T_19.1 ; + %load/vec4 v0x55cf9da63c10_0; + %store/vec4 v0x55cf9da2bb00_0, 0, 8; + %jmp T_19.2; +T_19.2 ; + %pop/vec4 1; + %jmp T_19; + .thread T_19, $push; + .scope S_0x55cf9da2bc40; +T_20 ; + %wait E_0x55cf9da30600; + %load/vec4 v0x55cf9da30680_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_20.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_20.1, 6; + %jmp T_20.2; +T_20.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9da2e240_0, 0, 8; + %jmp T_20.2; +T_20.1 ; + %load/vec4 v0x55cf9da2be20_0; + %store/vec4 v0x55cf9da2e240_0, 0, 8; + %jmp T_20.2; +T_20.2 ; + %pop/vec4 1; + %jmp T_20; + .thread T_20, $push; + .scope S_0x55cf9da2e360; +T_21 ; + %wait E_0x55cf9da408b0; + %load/vec4 v0x55cf9da40930_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_21.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_21.1, 6; + %jmp T_21.2; +T_21.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9d9b4310_0, 0, 8; + %jmp T_21.2; +T_21.1 ; + %load/vec4 v0x55cf9da409f0_0; + %store/vec4 v0x55cf9d9b4310_0, 0, 8; + %jmp T_21.2; +T_21.2 ; + %pop/vec4 1; + %jmp T_21; + .thread T_21, $push; + .scope S_0x55cf9d9b4470; +T_22 ; + %wait E_0x55cf9d94e780; + %load/vec4 v0x55cf9d94e800_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_22.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_22.1, 6; + %jmp T_22.2; +T_22.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9d975290_0, 0, 8; + %jmp T_22.2; +T_22.1 ; + %load/vec4 v0x55cf9d9b4600_0; + %store/vec4 v0x55cf9d975290_0, 0, 8; + %jmp T_22.2; +T_22.2 ; + %pop/vec4 1; + %jmp T_22; + .thread T_22, $push; + .scope S_0x55cf9d9753b0; +T_23 ; + %wait E_0x55cf9da22b30; + %load/vec4 v0x55cf9da22bb0_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_23.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_23.1, 6; + %jmp T_23.2; +T_23.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9d9b4d60_0, 0, 8; + %jmp T_23.2; +T_23.1 ; + %load/vec4 v0x55cf9da22d00_0; + %store/vec4 v0x55cf9d9b4d60_0, 0, 8; + %jmp T_23.2; +T_23.2 ; + %pop/vec4 1; + %jmp T_23; + .thread T_23, $push; + .scope S_0x55cf9d9b4ea0; +T_24 ; + %wait E_0x55cf9da22dc0; + %load/vec4 v0x55cf9da2a440_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_24.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_24.1, 6; + %jmp T_24.2; +T_24.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9da25470_0, 0, 8; + %jmp T_24.2; +T_24.1 ; + %load/vec4 v0x55cf9da2a500_0; + %store/vec4 v0x55cf9da25470_0, 0, 8; + %jmp T_24.2; +T_24.2 ; + %pop/vec4 1; + %jmp T_24; + .thread T_24, $push; + .scope S_0x55cf9db90440; +T_25 ; + %wait E_0x55cf9d9495c0; + %load/vec4 v0x55cf9db7d5d0_0; + %load/vec4 v0x55cf9db760d0_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55cf9db76db0_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55cf9db77af0_0; + %concat/vec4; draw_concat_vec4 + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_25.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_25.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_25.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_25.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_25.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_25.5, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_25.6, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_25.7, 6; + %pushi/vec4 0, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9db7c8f0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7bc10_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7af30_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7afd0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7a250_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7a2f0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db79540_0, 0, 1; + %store/vec4 v0x55cf9db78830_0, 0, 1; + %jmp T_25.9; +T_25.0 ; + %pushi/vec4 1, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9db7c8f0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7bc10_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7af30_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7afd0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7a250_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7a2f0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db79540_0, 0, 1; + %store/vec4 v0x55cf9db78830_0, 0, 1; + %jmp T_25.9; +T_25.1 ; + %pushi/vec4 2, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9db7c8f0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7bc10_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7af30_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7afd0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7a250_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7a2f0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db79540_0, 0, 1; + %store/vec4 v0x55cf9db78830_0, 0, 1; + %jmp T_25.9; +T_25.2 ; + %pushi/vec4 4, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9db7c8f0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7bc10_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7af30_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7afd0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7a250_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7a2f0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db79540_0, 0, 1; + %store/vec4 v0x55cf9db78830_0, 0, 1; + %jmp T_25.9; +T_25.3 ; + %pushi/vec4 8, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9db7c8f0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7bc10_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7af30_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7afd0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7a250_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7a2f0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db79540_0, 0, 1; + %store/vec4 v0x55cf9db78830_0, 0, 1; + %jmp T_25.9; +T_25.4 ; + %pushi/vec4 16, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9db7c8f0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7bc10_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7af30_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7afd0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7a250_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7a2f0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db79540_0, 0, 1; + %store/vec4 v0x55cf9db78830_0, 0, 1; + %jmp T_25.9; +T_25.5 ; + %pushi/vec4 32, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9db7c8f0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7bc10_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7af30_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7afd0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7a250_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7a2f0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db79540_0, 0, 1; + %store/vec4 v0x55cf9db78830_0, 0, 1; + %jmp T_25.9; +T_25.6 ; + %pushi/vec4 64, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9db7c8f0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7bc10_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7af30_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7afd0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7a250_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7a2f0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db79540_0, 0, 1; + %store/vec4 v0x55cf9db78830_0, 0, 1; + %jmp T_25.9; +T_25.7 ; + %pushi/vec4 128, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9db7c8f0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7bc10_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7af30_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7afd0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7a250_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db7a2f0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9db79540_0, 0, 1; + %store/vec4 v0x55cf9db78830_0, 0, 1; + %jmp T_25.9; +T_25.9 ; + %pop/vec4 1; + %jmp T_25; + .thread T_25, $push; + .scope S_0x55cf9dbd3900; +T_26 ; + %wait E_0x55cf9dbd3d60; + %load/vec4 v0x55cf9dbd3de0_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_26.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_26.1, 6; + %jmp T_26.2; +T_26.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbd4060_0, 0, 8; + %jmp T_26.2; +T_26.1 ; + %load/vec4 v0x55cf9dbd3ed0_0; + %store/vec4 v0x55cf9dbd4060_0, 0, 8; + %jmp T_26.2; +T_26.2 ; + %pop/vec4 1; + %jmp T_26; + .thread T_26, $push; + .scope S_0x55cf9dbd41c0; +T_27 ; + %wait E_0x55cf9dbd4670; + %load/vec4 v0x55cf9dbd46f0_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_27.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_27.1, 6; + %jmp T_27.2; +T_27.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbd4a10_0, 0, 8; + %jmp T_27.2; +T_27.1 ; + %load/vec4 v0x55cf9dbd4800_0; + %store/vec4 v0x55cf9dbd4a10_0, 0, 8; + %jmp T_27.2; +T_27.2 ; + %pop/vec4 1; + %jmp T_27; + .thread T_27, $push; + .scope S_0x55cf9dbd5460; +T_28 ; + %wait E_0x55cf9dbd5910; + %load/vec4 v0x55cf9dbd5990_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_28.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_28.1, 6; + %jmp T_28.2; +T_28.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbd5c20_0, 0, 8; + %jmp T_28.2; +T_28.1 ; + %load/vec4 v0x55cf9dbd5a50_0; + %store/vec4 v0x55cf9dbd5c20_0, 0, 8; + %jmp T_28.2; +T_28.2 ; + %pop/vec4 1; + %jmp T_28; + .thread T_28, $push; + .scope S_0x55cf9dbd5d80; +T_29 ; + %wait E_0x55cf9d95e730; + %load/vec4 v0x55cf9dbd6230_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_29.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_29.1, 6; + %jmp T_29.2; +T_29.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbd6530_0, 0, 8; + %jmp T_29.2; +T_29.1 ; + %load/vec4 v0x55cf9dbd6380_0; + %store/vec4 v0x55cf9dbd6530_0, 0, 8; + %jmp T_29.2; +T_29.2 ; + %pop/vec4 1; + %jmp T_29; + .thread T_29, $push; + .scope S_0x55cf9dbd6690; +T_30 ; + %wait E_0x55cf9dbd5020; + %load/vec4 v0x55cf9dbd6af0_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_30.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_30.1, 6; + %jmp T_30.2; +T_30.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbd6d60_0, 0, 8; + %jmp T_30.2; +T_30.1 ; + %load/vec4 v0x55cf9dbd6bb0_0; + %store/vec4 v0x55cf9dbd6d60_0, 0, 8; + %jmp T_30.2; +T_30.2 ; + %pop/vec4 1; + %jmp T_30; + .thread T_30, $push; + .scope S_0x55cf9dbd6ec0; +T_31 ; + %wait E_0x55cf9dbd7370; + %load/vec4 v0x55cf9dbd73f0_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_31.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_31.1, 6; + %jmp T_31.2; +T_31.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbd7680_0, 0, 8; + %jmp T_31.2; +T_31.1 ; + %load/vec4 v0x55cf9dbd74b0_0; + %store/vec4 v0x55cf9dbd7680_0, 0, 8; + %jmp T_31.2; +T_31.2 ; + %pop/vec4 1; + %jmp T_31; + .thread T_31, $push; + .scope S_0x55cf9dbd77e0; +T_32 ; + %wait E_0x55cf9dbd7c90; + %load/vec4 v0x55cf9dbd7d10_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_32.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_32.1, 6; + %jmp T_32.2; +T_32.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbd7fa0_0, 0, 8; + %jmp T_32.2; +T_32.1 ; + %load/vec4 v0x55cf9dbd7e00_0; + %store/vec4 v0x55cf9dbd7fa0_0, 0, 8; + %jmp T_32.2; +T_32.2 ; + %pop/vec4 1; + %jmp T_32; + .thread T_32, $push; + .scope S_0x55cf9dbd80e0; +T_33 ; + %wait E_0x55cf9dbd8590; + %load/vec4 v0x55cf9dbd8610_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_33.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_33.1, 6; + %jmp T_33.2; +T_33.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbd88b0_0, 0, 8; + %jmp T_33.2; +T_33.1 ; + %load/vec4 v0x55cf9dbd8720_0; + %store/vec4 v0x55cf9dbd88b0_0, 0, 8; + %jmp T_33.2; +T_33.2 ; + %pop/vec4 1; + %jmp T_33; + .thread T_33, $push; + .scope S_0x55cf9dbd8a10; +T_34 ; + %wait E_0x55cf9d9a9360; + %load/vec4 v0x55cf9dbd8ec0_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_34.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_34.1, 6; + %jmp T_34.2; +T_34.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbd91d0_0, 0, 8; + %jmp T_34.2; +T_34.1 ; + %load/vec4 v0x55cf9dbd9010_0; + %store/vec4 v0x55cf9dbd91d0_0, 0, 8; + %jmp T_34.2; +T_34.2 ; + %pop/vec4 1; + %jmp T_34; + .thread T_34, $push; + .scope S_0x55cf9dbd9310; +T_35 ; + %wait E_0x55cf9da05040; + %load/vec4 v0x55cf9dbd9770_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_35.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_35.1, 6; + %jmp T_35.2; +T_35.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbd99f0_0, 0, 8; + %jmp T_35.2; +T_35.1 ; + %load/vec4 v0x55cf9dbd9830_0; + %store/vec4 v0x55cf9dbd99f0_0, 0, 8; + %jmp T_35.2; +T_35.2 ; + %pop/vec4 1; + %jmp T_35; + .thread T_35, $push; + .scope S_0x55cf9dbd9b30; +T_36 ; + %wait E_0x55cf9dbd9fe0; + %load/vec4 v0x55cf9dbda060_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_36.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_36.1, 6; + %jmp T_36.2; +T_36.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbda2e0_0, 0, 8; + %jmp T_36.2; +T_36.1 ; + %load/vec4 v0x55cf9dbda120_0; + %store/vec4 v0x55cf9dbda2e0_0, 0, 8; + %jmp T_36.2; +T_36.2 ; + %pop/vec4 1; + %jmp T_36; + .thread T_36, $push; + .scope S_0x55cf9dbda440; +T_37 ; + %wait E_0x55cf9dbd5020; + %load/vec4 v0x55cf9dbda8f0_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_37.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_37.1, 6; + %jmp T_37.2; +T_37.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbdab70_0, 0, 8; + %jmp T_37.2; +T_37.1 ; + %load/vec4 v0x55cf9dbda9b0_0; + %store/vec4 v0x55cf9dbdab70_0, 0, 8; + %jmp T_37.2; +T_37.2 ; + %pop/vec4 1; + %jmp T_37; + .thread T_37, $push; + .scope S_0x55cf9dbdb5c0; +T_38 ; + %wait E_0x55cf9dbdbb80; + %load/vec4 v0x55cf9dbdbc00_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_38.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_38.1, 6; + %jmp T_38.2; +T_38.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbdbe80_0, 0, 8; + %jmp T_38.2; +T_38.1 ; + %load/vec4 v0x55cf9dbdbcc0_0; + %store/vec4 v0x55cf9dbdbe80_0, 0, 8; + %jmp T_38.2; +T_38.2 ; + %pop/vec4 1; + %jmp T_38; + .thread T_38, $push; + .scope S_0x55cf9dbdbfe0; +T_39 ; + %wait E_0x55cf9d971000; + %load/vec4 v0x55cf9dbdc490_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_39.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_39.1, 6; + %jmp T_39.2; +T_39.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbdc710_0, 0, 8; + %jmp T_39.2; +T_39.1 ; + %load/vec4 v0x55cf9dbdc550_0; + %store/vec4 v0x55cf9dbdc710_0, 0, 8; + %jmp T_39.2; +T_39.2 ; + %pop/vec4 1; + %jmp T_39; + .thread T_39, $push; + .scope S_0x55cf9dbdc850; +T_40 ; + %wait E_0x55cf9da30600; + %load/vec4 v0x55cf9dbdcd00_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_40.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_40.1, 6; + %jmp T_40.2; +T_40.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbdcf80_0, 0, 8; + %jmp T_40.2; +T_40.1 ; + %load/vec4 v0x55cf9dbdcdc0_0; + %store/vec4 v0x55cf9dbdcf80_0, 0, 8; + %jmp T_40.2; +T_40.2 ; + %pop/vec4 1; + %jmp T_40; + .thread T_40, $push; + .scope S_0x55cf9dbdd0c0; +T_41 ; + %wait E_0x55cf9da63b20; + %load/vec4 v0x55cf9dbdd680_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_41.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_41.1, 6; + %jmp T_41.2; +T_41.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbdd900_0, 0, 8; + %jmp T_41.2; +T_41.1 ; + %load/vec4 v0x55cf9dbdd740_0; + %store/vec4 v0x55cf9dbdd900_0, 0, 8; + %jmp T_41.2; +T_41.2 ; + %pop/vec4 1; + %jmp T_41; + .thread T_41, $push; + .scope S_0x55cf9dbdda40; +T_42 ; + %wait E_0x55cf9dbddef0; + %load/vec4 v0x55cf9dbddf70_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_42.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_42.1, 6; + %jmp T_42.2; +T_42.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbde1f0_0, 0, 8; + %jmp T_42.2; +T_42.1 ; + %load/vec4 v0x55cf9dbde030_0; + %store/vec4 v0x55cf9dbde1f0_0, 0, 8; + %jmp T_42.2; +T_42.2 ; + %pop/vec4 1; + %jmp T_42; + .thread T_42, $push; + .scope S_0x55cf9dbde350; +T_43 ; + %wait E_0x55cf9dbde800; + %load/vec4 v0x55cf9dbde880_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_43.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_43.1, 6; + %jmp T_43.2; +T_43.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbdeb00_0, 0, 8; + %jmp T_43.2; +T_43.1 ; + %load/vec4 v0x55cf9dbde940_0; + %store/vec4 v0x55cf9dbdeb00_0, 0, 8; + %jmp T_43.2; +T_43.2 ; + %pop/vec4 1; + %jmp T_43; + .thread T_43, $push; + .scope S_0x55cf9dbdec60; +T_44 ; + %wait E_0x55cf9dbdf110; + %load/vec4 v0x55cf9dbdf190_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_44.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_44.1, 6; + %jmp T_44.2; +T_44.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbdf410_0, 0, 8; + %jmp T_44.2; +T_44.1 ; + %load/vec4 v0x55cf9dbdf250_0; + %store/vec4 v0x55cf9dbdf410_0, 0, 8; + %jmp T_44.2; +T_44.2 ; + %pop/vec4 1; + %jmp T_44; + .thread T_44, $push; + .scope S_0x55cf9dbdf570; +T_45 ; + %wait E_0x55cf9dbdfa20; + %load/vec4 v0x55cf9dbdfaa0_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_45.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_45.1, 6; + %jmp T_45.2; +T_45.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbdfd20_0, 0, 8; + %jmp T_45.2; +T_45.1 ; + %load/vec4 v0x55cf9dbdfb60_0; + %store/vec4 v0x55cf9dbdfd20_0, 0, 8; + %jmp T_45.2; +T_45.2 ; + %pop/vec4 1; + %jmp T_45; + .thread T_45, $push; + .scope S_0x55cf9dbdfe80; +T_46 ; + %wait E_0x55cf9d9a9360; + %load/vec4 v0x55cf9dbe0440_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_46.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_46.1, 6; + %jmp T_46.2; +T_46.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbe06c0_0, 0, 8; + %jmp T_46.2; +T_46.1 ; + %load/vec4 v0x55cf9dbe0500_0; + %store/vec4 v0x55cf9dbe06c0_0, 0, 8; + %jmp T_46.2; +T_46.2 ; + %pop/vec4 1; + %jmp T_46; + .thread T_46, $push; + .scope S_0x55cf9dbe0820; +T_47 ; + %wait E_0x55cf9da05040; + %load/vec4 v0x55cf9dbe0cd0_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_47.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_47.1, 6; + %jmp T_47.2; +T_47.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbe0f20_0, 0, 8; + %jmp T_47.2; +T_47.1 ; + %load/vec4 v0x55cf9dbe0d90_0; + %store/vec4 v0x55cf9dbe0f20_0, 0, 8; + %jmp T_47.2; +T_47.2 ; + %pop/vec4 1; + %jmp T_47; + .thread T_47, $push; + .scope S_0x55cf9dbe1060; +T_48 ; + %wait E_0x55cf9da27240; + %load/vec4 v0x55cf9dbe1620_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_48.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_48.1, 6; + %jmp T_48.2; +T_48.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbe18a0_0, 0, 8; + %jmp T_48.2; +T_48.1 ; + %load/vec4 v0x55cf9dbe16e0_0; + %store/vec4 v0x55cf9dbe18a0_0, 0, 8; + %jmp T_48.2; +T_48.2 ; + %pop/vec4 1; + %jmp T_48; + .thread T_48, $push; + .scope S_0x55cf9dbe19e0; +T_49 ; + %wait E_0x55cf9d971000; + %load/vec4 v0x55cf9dbe23b0_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_49.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_49.1, 6; + %jmp T_49.2; +T_49.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbe2630_0, 0, 8; + %jmp T_49.2; +T_49.1 ; + %load/vec4 v0x55cf9dbe2470_0; + %store/vec4 v0x55cf9dbe2630_0, 0, 8; + %jmp T_49.2; +T_49.2 ; + %pop/vec4 1; + %jmp T_49; + .thread T_49, $push; + .scope S_0x55cf9dbe2770; +T_50 ; + %wait E_0x55cf9da63b20; + %load/vec4 v0x55cf9dbe2c20_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_50.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_50.1, 6; + %jmp T_50.2; +T_50.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbe2ea0_0, 0, 8; + %jmp T_50.2; +T_50.1 ; + %load/vec4 v0x55cf9dbe2ce0_0; + %store/vec4 v0x55cf9dbe2ea0_0, 0, 8; + %jmp T_50.2; +T_50.2 ; + %pop/vec4 1; + %jmp T_50; + .thread T_50, $push; + .scope S_0x55cf9dbe2fe0; +T_51 ; + %wait E_0x55cf9d94e780; + %load/vec4 v0x55cf9dbe3490_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_51.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_51.1, 6; + %jmp T_51.2; +T_51.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbe3710_0, 0, 8; + %jmp T_51.2; +T_51.1 ; + %load/vec4 v0x55cf9dbe3550_0; + %store/vec4 v0x55cf9dbe3710_0, 0, 8; + %jmp T_51.2; +T_51.2 ; + %pop/vec4 1; + %jmp T_51; + .thread T_51, $push; + .scope S_0x55cf9dbe3870; +T_52 ; + %wait E_0x55cf9da22b30; + %load/vec4 v0x55cf9dbe3d20_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_52.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_52.1, 6; + %jmp T_52.2; +T_52.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbe3f70_0, 0, 8; + %jmp T_52.2; +T_52.1 ; + %load/vec4 v0x55cf9dbe3de0_0; + %store/vec4 v0x55cf9dbe3f70_0, 0, 8; + %jmp T_52.2; +T_52.2 ; + %pop/vec4 1; + %jmp T_52; + .thread T_52, $push; + .scope S_0x55cf9dbe40b0; +T_53 ; + %wait E_0x55cf9da30600; + %load/vec4 v0x55cf9dbe4560_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_53.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_53.1, 6; + %jmp T_53.2; +T_53.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbe47e0_0, 0, 8; + %jmp T_53.2; +T_53.1 ; + %load/vec4 v0x55cf9dbe4620_0; + %store/vec4 v0x55cf9dbe47e0_0, 0, 8; + %jmp T_53.2; +T_53.2 ; + %pop/vec4 1; + %jmp T_53; + .thread T_53, $push; + .scope S_0x55cf9dbe4920; +T_54 ; + %wait E_0x55cf9dbe4dd0; + %load/vec4 v0x55cf9dbe4e50_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_54.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_54.1, 6; + %jmp T_54.2; +T_54.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbe50d0_0, 0, 8; + %jmp T_54.2; +T_54.1 ; + %load/vec4 v0x55cf9dbe4f10_0; + %store/vec4 v0x55cf9dbe50d0_0, 0, 8; + %jmp T_54.2; +T_54.2 ; + %pop/vec4 1; + %jmp T_54; + .thread T_54, $push; + .scope S_0x55cf9dbe5230; +T_55 ; + %wait E_0x55cf9dbe56e0; + %load/vec4 v0x55cf9dbe5760_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_55.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_55.1, 6; + %jmp T_55.2; +T_55.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbe59e0_0, 0, 8; + %jmp T_55.2; +T_55.1 ; + %load/vec4 v0x55cf9dbe5820_0; + %store/vec4 v0x55cf9dbe59e0_0, 0, 8; + %jmp T_55.2; +T_55.2 ; + %pop/vec4 1; + %jmp T_55; + .thread T_55, $push; + .scope S_0x55cf9dbe5b40; +T_56 ; + %wait E_0x55cf9dbe5ff0; + %load/vec4 v0x55cf9dbe6070_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_56.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_56.1, 6; + %jmp T_56.2; +T_56.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbe62f0_0, 0, 8; + %jmp T_56.2; +T_56.1 ; + %load/vec4 v0x55cf9dbe6130_0; + %store/vec4 v0x55cf9dbe62f0_0, 0, 8; + %jmp T_56.2; +T_56.2 ; + %pop/vec4 1; + %jmp T_56; + .thread T_56, $push; + .scope S_0x55cf9dbe6450; +T_57 ; + %wait E_0x55cf9dbe6900; + %load/vec4 v0x55cf9dbe6980_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_57.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_57.1, 6; + %jmp T_57.2; +T_57.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbe6c00_0, 0, 8; + %jmp T_57.2; +T_57.1 ; + %load/vec4 v0x55cf9dbe6a40_0; + %store/vec4 v0x55cf9dbe6c00_0, 0, 8; + %jmp T_57.2; +T_57.2 ; + %pop/vec4 1; + %jmp T_57; + .thread T_57, $push; + .scope S_0x55cf9da07d00; +T_58 ; + %wait E_0x55cf9db563c0; + %load/vec4 v0x55cf9d96f0d0_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_58.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_58.1, 6; + %jmp T_58.2; +T_58.0 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x55cf9da26ff0_0, 0, 1; + %jmp T_58.2; +T_58.1 ; + %load/vec4 v0x55cf9da26e50_0; + %store/vec4 v0x55cf9da26ff0_0, 0, 1; + %jmp T_58.2; +T_58.2 ; + %pop/vec4 1; + %jmp T_58; + .thread T_58, $push; + .scope S_0x55cf9da44c70; +T_59 ; + %wait E_0x55cf9db6c670; + %load/vec4 v0x55cf9da27150_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_59.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_59.1, 6; + %jmp T_59.2; +T_59.0 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x55cf9da21350_0, 0, 1; + %jmp T_59.2; +T_59.1 ; + %load/vec4 v0x55cf9da211b0_0; + %store/vec4 v0x55cf9da21350_0, 0, 1; + %jmp T_59.2; +T_59.2 ; + %pop/vec4 1; + %jmp T_59; + .thread T_59, $push; + .scope S_0x55cf9dba30d0; +T_60 ; + %wait E_0x55cf9db556b0; + %load/vec4 v0x55cf9db8b2a0_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_60.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_60.1, 6; + %jmp T_60.2; +T_60.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9db59750_0, 0, 8; + %jmp T_60.2; +T_60.1 ; + %load/vec4 v0x55cf9db4ce90_0; + %store/vec4 v0x55cf9db59750_0, 0, 8; + %jmp T_60.2; +T_60.2 ; + %pop/vec4 1; + %jmp T_60; + .thread T_60, $push; + .scope S_0x55cf9dbe6d60; +T_61 ; + %wait E_0x55cf9dbe7320; + %load/vec4 v0x55cf9dbe73a0_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_61.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_61.1, 6; + %jmp T_61.2; +T_61.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbe7640_0, 0, 8; + %jmp T_61.2; +T_61.1 ; + %load/vec4 v0x55cf9dbe7490_0; + %store/vec4 v0x55cf9dbe7640_0, 0, 8; + %jmp T_61.2; +T_61.2 ; + %pop/vec4 1; + %jmp T_61; + .thread T_61, $push; + .scope S_0x55cf9dbe77a0; +T_62 ; + %wait E_0x55cf9dbe7c50; + %load/vec4 v0x55cf9dbe7cd0_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_62.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_62.1, 6; + %jmp T_62.2; +T_62.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbe7f80_0, 0, 8; + %jmp T_62.2; +T_62.1 ; + %load/vec4 v0x55cf9dbe7de0_0; + %store/vec4 v0x55cf9dbe7f80_0, 0, 8; + %jmp T_62.2; +T_62.2 ; + %pop/vec4 1; + %jmp T_62; + .thread T_62, $push; + .scope S_0x55cf9dbe80e0; +T_63 ; + %wait E_0x55cf9dbe8590; + %load/vec4 v0x55cf9dbe8610_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_63.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_63.1, 6; + %jmp T_63.2; +T_63.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbe88b0_0, 0, 8; + %jmp T_63.2; +T_63.1 ; + %load/vec4 v0x55cf9dbe8700_0; + %store/vec4 v0x55cf9dbe88b0_0, 0, 8; + %jmp T_63.2; +T_63.2 ; + %pop/vec4 1; + %jmp T_63; + .thread T_63, $push; + .scope S_0x55cf9dbe8a10; +T_64 ; + %wait E_0x55cf9da27240; + %load/vec4 v0x55cf9dbe8ec0_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_64.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_64.1, 6; + %jmp T_64.2; +T_64.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dbe9130_0, 0, 8; + %jmp T_64.2; +T_64.1 ; + %load/vec4 v0x55cf9dbe8f80_0; + %store/vec4 v0x55cf9dbe9130_0, 0, 8; + %jmp T_64.2; +T_64.2 ; + %pop/vec4 1; + %jmp T_64; + .thread T_64, $push; + .scope S_0x55cf9dc118e0; +T_65 ; + %wait E_0x55cf9dc11ae0; + %load/vec4 v0x55cf9dc12190_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_65.2, 9; + %load/vec4 v0x55cf9dc12690_0; + %nor/r; + %and; +T_65.2; + %flag_set/vec4 8; + %jmp/0xz T_65.0, 8; + %pushi/vec4 0, 0, 56; + %ix/getv 4, v0x55cf9dc11b60_0; + %load/vec4a v0x55cf9dc12250, 4; + %concat/vec4; draw_concat_vec4 + %store/vec4 v0x55cf9dc12310_0, 0, 64; + %jmp T_65.1; +T_65.0 ; + %pushi/vec4 0, 0, 64; + %store/vec4 v0x55cf9dc12310_0, 0, 64; +T_65.1 ; + %pushi/vec4 0, 0, 64; + %store/vec4 v0x55cf9dc123f0_0, 0, 64; + %pushi/vec4 0, 0, 64; + %store/vec4 v0x55cf9dc124d0_0, 0, 64; + %pushi/vec4 0, 0, 64; + %store/vec4 v0x55cf9dc125b0_0, 0, 64; + %jmp T_65; + .thread T_65, $push; + .scope S_0x55cf9dc118e0; +T_66 ; + %wait E_0x55cf9dc0b6a0; + %load/vec4 v0x55cf9dc12690_0; + %flag_set/vec4 8; + %jmp/0xz T_66.0, 8; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x55cf9dc11d20_0, 0, 32; +T_66.2 ; + %load/vec4 v0x55cf9dc11d20_0; + %pad/u 64; + %cmpi/u 64, 0, 64; + %jmp/0xz T_66.3, 5; + %pushi/vec4 0, 0, 8; + %ix/getv/s 4, v0x55cf9dc11d20_0; + %store/vec4a v0x55cf9dc12250, 4, 0; + %load/vec4 v0x55cf9dc11d20_0; + %addi 1, 0, 32; + %store/vec4 v0x55cf9dc11d20_0, 0, 32; + %jmp T_66.2; +T_66.3 ; + %jmp T_66.1; +T_66.0 ; + %load/vec4 v0x55cf9dc12730_0; + %flag_set/vec4 8; + %jmp/0xz T_66.4, 8; + %load/vec4 v0x55cf9dc11dc0_0; + %parti/s 8, 0, 2; + %ix/getv 4, v0x55cf9dc11b60_0; + %store/vec4a v0x55cf9dc12250, 4, 0; +T_66.4 ; +T_66.1 ; + %jmp T_66; + .thread T_66; + .scope S_0x55cf9dc11300; +T_67 ; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x55cf9dc11d20_0, 0, 32; +T_67.0 ; + %load/vec4 v0x55cf9dc11d20_0; + %pad/u 64; + %cmpi/u 64, 0, 64; + %jmp/0xz T_67.1, 5; + %pushi/vec4 0, 0, 8; + %ix/getv/s 4, v0x55cf9dc11d20_0; + %store/vec4a v0x55cf9dc12250, 4, 0; + %load/vec4 v0x55cf9dc11d20_0; + %addi 1, 0, 32; + %store/vec4 v0x55cf9dc11d20_0, 0, 32; + %jmp T_67.0; +T_67.1 ; + %pushi/vec4 0, 0, 64; + %store/vec4 v0x55cf9dc12310_0, 0, 64; + %pushi/vec4 0, 0, 64; + %store/vec4 v0x55cf9dc123f0_0, 0, 64; + %pushi/vec4 0, 0, 64; + %store/vec4 v0x55cf9dc124d0_0, 0, 64; + %pushi/vec4 0, 0, 64; + %store/vec4 v0x55cf9dc125b0_0, 0, 64; + %end; + .thread T_67; + .scope S_0x55cf9dc09200; +T_68 ; + %wait E_0x55cf9dc06e10; + %load/vec4 v0x55cf9dc096d0_0; + %load/vec4 v0x55cf9dc09fe0_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55cf9dc09f20_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55cf9dc09e60_0; + %concat/vec4; draw_concat_vec4 + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_68.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_68.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_68.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_68.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_68.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_68.5, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_68.6, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_68.7, 6; + %pushi/vec4 0, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9dc097b0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09870_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09940_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09a00_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09b10_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09bd0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09c90_0, 0, 1; + %store/vec4 v0x55cf9dc09d30_0, 0, 1; + %jmp T_68.9; +T_68.0 ; + %pushi/vec4 1, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9dc097b0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09870_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09940_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09a00_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09b10_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09bd0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09c90_0, 0, 1; + %store/vec4 v0x55cf9dc09d30_0, 0, 1; + %jmp T_68.9; +T_68.1 ; + %pushi/vec4 2, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9dc097b0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09870_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09940_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09a00_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09b10_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09bd0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09c90_0, 0, 1; + %store/vec4 v0x55cf9dc09d30_0, 0, 1; + %jmp T_68.9; +T_68.2 ; + %pushi/vec4 4, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9dc097b0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09870_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09940_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09a00_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09b10_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09bd0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09c90_0, 0, 1; + %store/vec4 v0x55cf9dc09d30_0, 0, 1; + %jmp T_68.9; +T_68.3 ; + %pushi/vec4 8, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9dc097b0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09870_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09940_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09a00_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09b10_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09bd0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09c90_0, 0, 1; + %store/vec4 v0x55cf9dc09d30_0, 0, 1; + %jmp T_68.9; +T_68.4 ; + %pushi/vec4 16, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9dc097b0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09870_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09940_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09a00_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09b10_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09bd0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09c90_0, 0, 1; + %store/vec4 v0x55cf9dc09d30_0, 0, 1; + %jmp T_68.9; +T_68.5 ; + %pushi/vec4 32, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9dc097b0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09870_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09940_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09a00_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09b10_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09bd0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09c90_0, 0, 1; + %store/vec4 v0x55cf9dc09d30_0, 0, 1; + %jmp T_68.9; +T_68.6 ; + %pushi/vec4 64, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9dc097b0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09870_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09940_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09a00_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09b10_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09bd0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09c90_0, 0, 1; + %store/vec4 v0x55cf9dc09d30_0, 0, 1; + %jmp T_68.9; +T_68.7 ; + %pushi/vec4 128, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9dc097b0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09870_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09940_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09a00_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09b10_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09bd0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc09c90_0, 0, 1; + %store/vec4 v0x55cf9dc09d30_0, 0, 1; + %jmp T_68.9; +T_68.9 ; + %pop/vec4 1; + %jmp T_68; + .thread T_68, $push; + .scope S_0x55cf9dc0a220; +T_69 ; + %wait E_0x55cf9dc0a680; + %load/vec4 v0x55cf9dc0a710_0; + %load/vec4 v0x55cf9dc0b010_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55cf9dc0af50_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55cf9dc0ae90_0; + %concat/vec4; draw_concat_vec4 + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_69.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_69.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_69.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_69.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_69.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_69.5, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_69.6, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_69.7, 6; + %pushi/vec4 0, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9dc0a800_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0a8a0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0a970_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0aa30_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0ab40_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0ac00_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0acc0_0, 0, 1; + %store/vec4 v0x55cf9dc0ad60_0, 0, 1; + %jmp T_69.9; +T_69.0 ; + %pushi/vec4 1, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9dc0a800_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0a8a0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0a970_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0aa30_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0ab40_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0ac00_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0acc0_0, 0, 1; + %store/vec4 v0x55cf9dc0ad60_0, 0, 1; + %jmp T_69.9; +T_69.1 ; + %pushi/vec4 2, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9dc0a800_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0a8a0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0a970_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0aa30_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0ab40_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0ac00_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0acc0_0, 0, 1; + %store/vec4 v0x55cf9dc0ad60_0, 0, 1; + %jmp T_69.9; +T_69.2 ; + %pushi/vec4 4, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9dc0a800_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0a8a0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0a970_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0aa30_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0ab40_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0ac00_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0acc0_0, 0, 1; + %store/vec4 v0x55cf9dc0ad60_0, 0, 1; + %jmp T_69.9; +T_69.3 ; + %pushi/vec4 8, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9dc0a800_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0a8a0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0a970_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0aa30_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0ab40_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0ac00_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0acc0_0, 0, 1; + %store/vec4 v0x55cf9dc0ad60_0, 0, 1; + %jmp T_69.9; +T_69.4 ; + %pushi/vec4 16, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9dc0a800_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0a8a0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0a970_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0aa30_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0ab40_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0ac00_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0acc0_0, 0, 1; + %store/vec4 v0x55cf9dc0ad60_0, 0, 1; + %jmp T_69.9; +T_69.5 ; + %pushi/vec4 32, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9dc0a800_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0a8a0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0a970_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0aa30_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0ab40_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0ac00_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0acc0_0, 0, 1; + %store/vec4 v0x55cf9dc0ad60_0, 0, 1; + %jmp T_69.9; +T_69.6 ; + %pushi/vec4 64, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9dc0a800_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0a8a0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0a970_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0aa30_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0ab40_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0ac00_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0acc0_0, 0, 1; + %store/vec4 v0x55cf9dc0ad60_0, 0, 1; + %jmp T_69.9; +T_69.7 ; + %pushi/vec4 128, 0, 8; + %split/vec4 1; + %store/vec4 v0x55cf9dc0a800_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0a8a0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0a970_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0aa30_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0ab40_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0ac00_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc0acc0_0, 0, 1; + %store/vec4 v0x55cf9dc0ad60_0, 0, 1; + %jmp T_69.9; +T_69.9 ; + %pop/vec4 1; + %jmp T_69; + .thread T_69, $push; + .scope S_0x55cf9dc26620; +T_70 ; + %wait E_0x55cf9dc26ad0; + %load/vec4 v0x55cf9dc26b50_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_70.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_70.1, 6; + %jmp T_70.2; +T_70.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc26dd0_0, 0, 8; + %jmp T_70.2; +T_70.1 ; + %load/vec4 v0x55cf9dc26c10_0; + %store/vec4 v0x55cf9dc26dd0_0, 0, 8; + %jmp T_70.2; +T_70.2 ; + %pop/vec4 1; + %jmp T_70; + .thread T_70, $push; + .scope S_0x55cf9dc26f30; +T_71 ; + %wait E_0x55cf9dc273e0; + %load/vec4 v0x55cf9dc27460_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_71.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_71.1, 6; + %jmp T_71.2; +T_71.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc27700_0, 0, 8; + %jmp T_71.2; +T_71.1 ; + %load/vec4 v0x55cf9dc27520_0; + %store/vec4 v0x55cf9dc27700_0, 0, 8; + %jmp T_71.2; +T_71.2 ; + %pop/vec4 1; + %jmp T_71; + .thread T_71, $push; + .scope S_0x55cf9dc27840; +T_72 ; + %wait E_0x55cf9dc27cf0; + %load/vec4 v0x55cf9dc27d70_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_72.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_72.1, 6; + %jmp T_72.2; +T_72.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc28000_0, 0, 8; + %jmp T_72.2; +T_72.1 ; + %load/vec4 v0x55cf9dc27e60_0; + %store/vec4 v0x55cf9dc28000_0, 0, 8; + %jmp T_72.2; +T_72.2 ; + %pop/vec4 1; + %jmp T_72; + .thread T_72, $push; + .scope S_0x55cf9dc28160; +T_73 ; + %wait E_0x55cf9dc28610; + %load/vec4 v0x55cf9dc28690_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_73.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_73.1, 6; + %jmp T_73.2; +T_73.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc28900_0, 0, 8; + %jmp T_73.2; +T_73.1 ; + %load/vec4 v0x55cf9dc28750_0; + %store/vec4 v0x55cf9dc28900_0, 0, 8; + %jmp T_73.2; +T_73.2 ; + %pop/vec4 1; + %jmp T_73; + .thread T_73, $push; + .scope S_0x55cf9dc28a60; +T_74 ; + %wait E_0x55cf9dc28f10; + %load/vec4 v0x55cf9dc28f90_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_74.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_74.1, 6; + %jmp T_74.2; +T_74.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc292a0_0, 0, 8; + %jmp T_74.2; +T_74.1 ; + %load/vec4 v0x55cf9dc290e0_0; + %store/vec4 v0x55cf9dc292a0_0, 0, 8; + %jmp T_74.2; +T_74.2 ; + %pop/vec4 1; + %jmp T_74; + .thread T_74, $push; + .scope S_0x55cf9dc29400; +T_75 ; + %wait E_0x55cf9dc29860; + %load/vec4 v0x55cf9dc298e0_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_75.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_75.1, 6; + %jmp T_75.2; +T_75.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc29c80_0, 0, 8; + %jmp T_75.2; +T_75.1 ; + %load/vec4 v0x55cf9dc29a30_0; + %store/vec4 v0x55cf9dc29c80_0, 0, 8; + %jmp T_75.2; +T_75.2 ; + %pop/vec4 1; + %jmp T_75; + .thread T_75, $push; + .scope S_0x55cf9dc05ef0; +T_76 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc06760_0, 0, 8; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc069e0_0, 0, 8; + %end; + .thread T_76; + .scope S_0x55cf9dc05ef0; +T_77 ; + %wait E_0x55cf9dc06510; + %load/vec4 v0x55cf9dc06800_0; + %flag_set/vec4 8; + %jmp/0xz T_77.0, 8; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x55cf9dc06760_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x55cf9dc069e0_0, 0; + %jmp T_77.1; +T_77.0 ; + %load/vec4 v0x55cf9dc068f0_0; + %flag_set/vec4 8; + %jmp/0xz T_77.2, 8; + %load/vec4 v0x55cf9dc066a0_0; + %assign/vec4 v0x55cf9dc06760_0, 0; + %load/vec4 v0x55cf9dc066a0_0; + %addi 1, 0, 8; + %assign/vec4 v0x55cf9dc069e0_0, 0; + %jmp T_77.3; +T_77.2 ; + %load/vec4 v0x55cf9dc069e0_0; + %assign/vec4 v0x55cf9dc06760_0, 0; + %load/vec4 v0x55cf9dc069e0_0; + %addi 1, 0, 8; + %assign/vec4 v0x55cf9dc069e0_0, 0; +T_77.3 ; +T_77.1 ; + %jmp T_77; + .thread T_77; + .scope S_0x55cf9dc29dc0; +T_78 ; + %wait E_0x55cf9dc2a1d0; + %load/vec4 v0x55cf9dc2a250_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_78.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_78.1, 6; + %jmp T_78.2; +T_78.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc2a4e0_0, 0, 8; + %jmp T_78.2; +T_78.1 ; + %load/vec4 v0x55cf9dc2a340_0; + %store/vec4 v0x55cf9dc2a4e0_0, 0, 8; + %jmp T_78.2; +T_78.2 ; + %pop/vec4 1; + %jmp T_78; + .thread T_78, $push; + .scope S_0x55cf9dc25470; +T_79 ; + %wait E_0x55cf9dc12d30; + %load/vec4 v0x55cf9dc25930_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_79.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_79.1, 6; + %jmp T_79.2; +T_79.0 ; + %pushi/vec4 0, 0, 16; + %store/vec4 v0x55cf9dc25be0_0, 0, 16; + %jmp T_79.2; +T_79.1 ; + %load/vec4 v0x55cf9dc259f0_0; + %store/vec4 v0x55cf9dc25be0_0, 0, 16; + %jmp T_79.2; +T_79.2 ; + %pop/vec4 1; + %jmp T_79; + .thread T_79, $push; + .scope S_0x55cf9dc13de0; +T_80 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc14600_0, 0, 8; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc14900_0, 0, 8; + %end; + .thread T_80; + .scope S_0x55cf9dc13de0; +T_81 ; + %wait E_0x55cf9dc14300; + %load/vec4 v0x55cf9dc14500_0; + %flag_set/vec4 8; + %jmp/0xz T_81.0, 8; + %load/vec4 v0x55cf9dc14900_0; + %assign/vec4 v0x55cf9dc14600_0, 0; + %jmp T_81.1; +T_81.0 ; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x55cf9dc14600_0, 0; +T_81.1 ; + %load/vec4 v0x55cf9dc147c0_0; + %assign/vec4 v0x55cf9dc146d0_0, 0; + %jmp T_81; + .thread T_81; + .scope S_0x55cf9dc13de0; +T_82 ; + %wait E_0x55cf9dc0b6a0; + %load/vec4 v0x55cf9dc146d0_0; + %flag_set/vec4 8; + %jmp/0xz T_82.0, 8; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x55cf9dc14900_0, 0; + %jmp T_82.1; +T_82.0 ; + %load/vec4 v0x55cf9dc14860_0; + %flag_set/vec4 8; + %jmp/0xz T_82.2, 8; + %load/vec4 v0x55cf9dc14420_0; + %assign/vec4 v0x55cf9dc14900_0, 0; +T_82.2 ; +T_82.1 ; + %jmp T_82; + .thread T_82; + .scope S_0x55cf9dc134d0; +T_83 ; + %wait E_0x55cf9dc13980; + %load/vec4 v0x55cf9dc13a00_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_83.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_83.1, 6; + %jmp T_83.2; +T_83.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc13c80_0, 0, 8; + %jmp T_83.2; +T_83.1 ; + %load/vec4 v0x55cf9dc13ae0_0; + %store/vec4 v0x55cf9dc13c80_0, 0, 8; + %jmp T_83.2; +T_83.2 ; + %pop/vec4 1; + %jmp T_83; + .thread T_83, $push; + .scope S_0x55cf9dc16af0; +T_84 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc17340_0, 0, 8; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc17640_0, 0, 8; + %end; + .thread T_84; + .scope S_0x55cf9dc16af0; +T_85 ; + %wait E_0x55cf9dc17040; + %load/vec4 v0x55cf9dc17240_0; + %flag_set/vec4 8; + %jmp/0xz T_85.0, 8; + %load/vec4 v0x55cf9dc17640_0; + %assign/vec4 v0x55cf9dc17340_0, 0; + %jmp T_85.1; +T_85.0 ; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x55cf9dc17340_0, 0; +T_85.1 ; + %load/vec4 v0x55cf9dc17500_0; + %assign/vec4 v0x55cf9dc17410_0, 0; + %jmp T_85; + .thread T_85; + .scope S_0x55cf9dc16af0; +T_86 ; + %wait E_0x55cf9dc0b6a0; + %load/vec4 v0x55cf9dc17410_0; + %flag_set/vec4 8; + %jmp/0xz T_86.0, 8; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x55cf9dc17640_0, 0; + %jmp T_86.1; +T_86.0 ; + %load/vec4 v0x55cf9dc175a0_0; + %flag_set/vec4 8; + %jmp/0xz T_86.2, 8; + %load/vec4 v0x55cf9dc17160_0; + %assign/vec4 v0x55cf9dc17640_0, 0; +T_86.2 ; +T_86.1 ; + %jmp T_86; + .thread T_86; + .scope S_0x55cf9dc161e0; +T_87 ; + %wait E_0x55cf9dc16690; + %load/vec4 v0x55cf9dc16710_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_87.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_87.1, 6; + %jmp T_87.2; +T_87.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc16990_0, 0, 8; + %jmp T_87.2; +T_87.1 ; + %load/vec4 v0x55cf9dc167f0_0; + %store/vec4 v0x55cf9dc16990_0, 0, 8; + %jmp T_87.2; +T_87.2 ; + %pop/vec4 1; + %jmp T_87; + .thread T_87, $push; + .scope S_0x55cf9dc19710; +T_88 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc19f60_0, 0, 8; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc1a260_0, 0, 8; + %end; + .thread T_88; + .scope S_0x55cf9dc19710; +T_89 ; + %wait E_0x55cf9dc19c60; + %load/vec4 v0x55cf9dc19e60_0; + %flag_set/vec4 8; + %jmp/0xz T_89.0, 8; + %load/vec4 v0x55cf9dc1a260_0; + %assign/vec4 v0x55cf9dc19f60_0, 0; + %jmp T_89.1; +T_89.0 ; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x55cf9dc19f60_0, 0; +T_89.1 ; + %load/vec4 v0x55cf9dc1a120_0; + %assign/vec4 v0x55cf9dc1a030_0, 0; + %jmp T_89; + .thread T_89; + .scope S_0x55cf9dc19710; +T_90 ; + %wait E_0x55cf9dc0b6a0; + %load/vec4 v0x55cf9dc1a030_0; + %flag_set/vec4 8; + %jmp/0xz T_90.0, 8; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x55cf9dc1a260_0, 0; + %jmp T_90.1; +T_90.0 ; + %load/vec4 v0x55cf9dc1a1c0_0; + %flag_set/vec4 8; + %jmp/0xz T_90.2, 8; + %load/vec4 v0x55cf9dc19d80_0; + %assign/vec4 v0x55cf9dc1a260_0, 0; +T_90.2 ; +T_90.1 ; + %jmp T_90; + .thread T_90; + .scope S_0x55cf9dc18e00; +T_91 ; + %wait E_0x55cf9dc192b0; + %load/vec4 v0x55cf9dc19330_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_91.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_91.1, 6; + %jmp T_91.2; +T_91.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc195b0_0, 0, 8; + %jmp T_91.2; +T_91.1 ; + %load/vec4 v0x55cf9dc19410_0; + %store/vec4 v0x55cf9dc195b0_0, 0, 8; + %jmp T_91.2; +T_91.2 ; + %pop/vec4 1; + %jmp T_91; + .thread T_91, $push; + .scope S_0x55cf9dc1c340; +T_92 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc1cb90_0, 0, 8; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc1ce90_0, 0, 8; + %end; + .thread T_92; + .scope S_0x55cf9dc1c340; +T_93 ; + %wait E_0x55cf9dc1c890; + %load/vec4 v0x55cf9dc1ca90_0; + %flag_set/vec4 8; + %jmp/0xz T_93.0, 8; + %load/vec4 v0x55cf9dc1ce90_0; + %assign/vec4 v0x55cf9dc1cb90_0, 0; + %jmp T_93.1; +T_93.0 ; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x55cf9dc1cb90_0, 0; +T_93.1 ; + %load/vec4 v0x55cf9dc1cd50_0; + %assign/vec4 v0x55cf9dc1cc60_0, 0; + %jmp T_93; + .thread T_93; + .scope S_0x55cf9dc1c340; +T_94 ; + %wait E_0x55cf9dc0b6a0; + %load/vec4 v0x55cf9dc1cc60_0; + %flag_set/vec4 8; + %jmp/0xz T_94.0, 8; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x55cf9dc1ce90_0, 0; + %jmp T_94.1; +T_94.0 ; + %load/vec4 v0x55cf9dc1cdf0_0; + %flag_set/vec4 8; + %jmp/0xz T_94.2, 8; + %load/vec4 v0x55cf9dc1c9b0_0; + %assign/vec4 v0x55cf9dc1ce90_0, 0; +T_94.2 ; +T_94.1 ; + %jmp T_94; + .thread T_94; + .scope S_0x55cf9dc1ba30; +T_95 ; + %wait E_0x55cf9dc1bee0; + %load/vec4 v0x55cf9dc1bf60_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_95.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_95.1, 6; + %jmp T_95.2; +T_95.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc1c1e0_0, 0, 8; + %jmp T_95.2; +T_95.1 ; + %load/vec4 v0x55cf9dc1c040_0; + %store/vec4 v0x55cf9dc1c1e0_0, 0, 8; + %jmp T_95.2; +T_95.2 ; + %pop/vec4 1; + %jmp T_95; + .thread T_95, $push; + .scope S_0x55cf9dc1ef60; +T_96 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc1f7b0_0, 0, 8; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc1fab0_0, 0, 8; + %end; + .thread T_96; + .scope S_0x55cf9dc1ef60; +T_97 ; + %wait E_0x55cf9dc1f4b0; + %load/vec4 v0x55cf9dc1f6b0_0; + %flag_set/vec4 8; + %jmp/0xz T_97.0, 8; + %load/vec4 v0x55cf9dc1fab0_0; + %assign/vec4 v0x55cf9dc1f7b0_0, 0; + %jmp T_97.1; +T_97.0 ; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x55cf9dc1f7b0_0, 0; +T_97.1 ; + %load/vec4 v0x55cf9dc1f970_0; + %assign/vec4 v0x55cf9dc1f880_0, 0; + %jmp T_97; + .thread T_97; + .scope S_0x55cf9dc1ef60; +T_98 ; + %wait E_0x55cf9dc0b6a0; + %load/vec4 v0x55cf9dc1f880_0; + %flag_set/vec4 8; + %jmp/0xz T_98.0, 8; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x55cf9dc1fab0_0, 0; + %jmp T_98.1; +T_98.0 ; + %load/vec4 v0x55cf9dc1fa10_0; + %flag_set/vec4 8; + %jmp/0xz T_98.2, 8; + %load/vec4 v0x55cf9dc1f5d0_0; + %assign/vec4 v0x55cf9dc1fab0_0, 0; +T_98.2 ; +T_98.1 ; + %jmp T_98; + .thread T_98; + .scope S_0x55cf9dc1e650; +T_99 ; + %wait E_0x55cf9dc1eb00; + %load/vec4 v0x55cf9dc1eb80_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_99.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_99.1, 6; + %jmp T_99.2; +T_99.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc1ee00_0, 0, 8; + %jmp T_99.2; +T_99.1 ; + %load/vec4 v0x55cf9dc1ec60_0; + %store/vec4 v0x55cf9dc1ee00_0, 0, 8; + %jmp T_99.2; +T_99.2 ; + %pop/vec4 1; + %jmp T_99; + .thread T_99, $push; + .scope S_0x55cf9dc21eb0; +T_100 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc22700_0, 0, 8; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc22a00_0, 0, 8; + %end; + .thread T_100; + .scope S_0x55cf9dc21eb0; +T_101 ; + %wait E_0x55cf9dc22400; + %load/vec4 v0x55cf9dc22600_0; + %flag_set/vec4 8; + %jmp/0xz T_101.0, 8; + %load/vec4 v0x55cf9dc22a00_0; + %assign/vec4 v0x55cf9dc22700_0, 0; + %jmp T_101.1; +T_101.0 ; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x55cf9dc22700_0, 0; +T_101.1 ; + %load/vec4 v0x55cf9dc228c0_0; + %assign/vec4 v0x55cf9dc227d0_0, 0; + %jmp T_101; + .thread T_101; + .scope S_0x55cf9dc21eb0; +T_102 ; + %wait E_0x55cf9dc0b6a0; + %load/vec4 v0x55cf9dc227d0_0; + %flag_set/vec4 8; + %jmp/0xz T_102.0, 8; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x55cf9dc22a00_0, 0; + %jmp T_102.1; +T_102.0 ; + %load/vec4 v0x55cf9dc22960_0; + %flag_set/vec4 8; + %jmp/0xz T_102.2, 8; + %load/vec4 v0x55cf9dc22520_0; + %assign/vec4 v0x55cf9dc22a00_0, 0; +T_102.2 ; +T_102.1 ; + %jmp T_102; + .thread T_102; + .scope S_0x55cf9dc215a0; +T_103 ; + %wait E_0x55cf9dc21a50; + %load/vec4 v0x55cf9dc21ad0_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_103.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_103.1, 6; + %jmp T_103.2; +T_103.0 ; + %pushi/vec4 0, 0, 8; + %store/vec4 v0x55cf9dc21d50_0, 0, 8; + %jmp T_103.2; +T_103.1 ; + %load/vec4 v0x55cf9dc21bb0_0; + %store/vec4 v0x55cf9dc21d50_0, 0, 8; + %jmp T_103.2; +T_103.2 ; + %pop/vec4 1; + %jmp T_103; + .thread T_103, $push; + .scope S_0x55cf9dc06f00; +T_104 ; + %wait E_0x55cf9dc07380; + %load/vec4 v0x55cf9dc07810_0; + %load/vec4 v0x55cf9dc07700_0; + %concat/vec4; draw_concat_vec4 + %dup/vec4; + %pushi/vec4 0, 0, 2; + %cmp/u; + %jmp/1 T_104.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_104.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 2; + %cmp/u; + %jmp/1 T_104.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 2; + %cmp/u; + %jmp/1 T_104.3, 6; + %jmp T_104.4; +T_104.0 ; + %pushi/vec4 1, 0, 4; + %split/vec4 1; + %store/vec4 v0x55cf9dc07400_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc074e0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc075a0_0, 0, 1; + %store/vec4 v0x55cf9dc07640_0, 0, 1; + %jmp T_104.4; +T_104.1 ; + %pushi/vec4 2, 0, 4; + %split/vec4 1; + %store/vec4 v0x55cf9dc07400_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc074e0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc075a0_0, 0, 1; + %store/vec4 v0x55cf9dc07640_0, 0, 1; + %jmp T_104.4; +T_104.2 ; + %pushi/vec4 4, 0, 4; + %split/vec4 1; + %store/vec4 v0x55cf9dc07400_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc074e0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc075a0_0, 0, 1; + %store/vec4 v0x55cf9dc07640_0, 0, 1; + %jmp T_104.4; +T_104.3 ; + %pushi/vec4 8, 0, 4; + %split/vec4 1; + %store/vec4 v0x55cf9dc07400_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc074e0_0, 0, 1; + %split/vec4 1; + %store/vec4 v0x55cf9dc075a0_0, 0, 1; + %store/vec4 v0x55cf9dc07640_0, 0, 1; + %jmp T_104.4; +T_104.4 ; + %pop/vec4 1; + %jmp T_104; + .thread T_104, $push; + .scope S_0x55cf9dc03140; +T_105 ; + %wait E_0x55cf9dc035f0; + %load/vec4 v0x55cf9dc03670_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_105.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_105.1, 6; + %jmp T_105.2; +T_105.0 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x55cf9dc03930_0, 0, 1; + %jmp T_105.2; +T_105.1 ; + %load/vec4 v0x55cf9dc03760_0; + %store/vec4 v0x55cf9dc03930_0, 0, 1; + %jmp T_105.2; +T_105.2 ; + %pop/vec4 1; + %jmp T_105; + .thread T_105, $push; + .scope S_0x55cf9dc02850; +T_106 ; + %wait E_0x55cf9dc02cd0; + %load/vec4 v0x55cf9dc02d50_0; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_106.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_106.1, 6; + %jmp T_106.2; +T_106.0 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x55cf9dc03000_0, 0, 1; + %jmp T_106.2; +T_106.1 ; + %load/vec4 v0x55cf9dc02e40_0; + %store/vec4 v0x55cf9dc03000_0, 0, 1; + %jmp T_106.2; +T_106.2 ; + %pop/vec4 1; + %jmp T_106; + .thread T_106, $push; + .scope S_0x55cf9db38d20; +T_107 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x55cf9dc31950_0, 0, 1; +T_107.0 ; + %delay 10, 0; + %load/vec4 v0x55cf9dc31950_0; + %inv; + %store/vec4 v0x55cf9dc31950_0, 0, 1; + %jmp T_107.0; + %end; + .thread T_107; + .scope S_0x55cf9db38d20; +T_108 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x55cf9dc32230_0, 0, 1; + %delay 50, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x55cf9dc32230_0, 0, 1; + %end; + .thread T_108; + .scope S_0x55cf9db38d20; +T_109 ; + %pushi/vec4 0, 0, 8; + %cassign/vec4 v0x55cf9dc31b70_0; + %vpi_func 2 45 "$value$plusargs" 32, "INPUT_FILE=%s", v0x55cf9dc31e40_0 {0 0 0}; + %store/vec4 v0x55cf9dc31f20_0, 0, 32; + %load/vec4 v0x55cf9dc31f20_0; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_109.0, 4; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x55cf9dc31f20_0, 0, 32; + %vpi_func 2 48 "$fopen" 32, v0x55cf9dc31e40_0, "r" {0 0 0}; + %store/vec4 v0x55cf9dc31da0_0, 0, 32; +T_109.2 ; + %load/vec4 v0x55cf9dc31f20_0; + %cmpi/s 65535, 0, 32; + %flag_get/vec4 5; + %jmp/0 T_109.4, 5; + %vpi_func 2 49 "$feof" 32, v0x55cf9dc31da0_0 {0 0 0}; + %nor/r; + %and; +T_109.4; + %flag_set/vec4 8; + %jmp/0xz T_109.3, 8; + %vpi_func 2 50 "$fgetc" 32, v0x55cf9dc31da0_0 {0 0 0}; + %pad/s 8; + %ix/getv/s 4, v0x55cf9dc31f20_0; + %store/vec4a v0x55cf9dc32170, 4, 0; + %jmp T_109.2; +T_109.3 ; +T_109.0 ; + %end; + .thread T_109; + .scope S_0x55cf9db38d20; +T_110 ; + %wait E_0x55cf9d9d4910; + %load/vec4 v0x55cf9dc32230_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_110.0, 8; + %load/vec4 v0x55cf9dc32000_0; + %pad/u 18; + %ix/vec4 4; + %load/vec4a v0x55cf9dc32170, 4; + %assign/vec4 v0x55cf9dc31b70_0, 0; + %load/vec4 v0x55cf9dc32000_0; + %addi 1, 0, 16; + %assign/vec4 v0x55cf9dc32000_0, 0; +T_110.0 ; + %jmp T_110; + .thread T_110; + .scope S_0x55cf9db38d20; +T_111 ; + %wait E_0x55cf9dc0b6a0; + %load/vec4 v0x55cf9dc31ad0_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_111.2, 9; + %load/vec4 v0x55cf9dc32230_0; + %nor/r; + %and; +T_111.2; + %flag_set/vec4 8; + %jmp/0xz T_111.0, 8; + %vpi_call 2 65 "$display", "received char 0x%h", v0x55cf9dc31c60_0 {0 0 0}; +T_111.0 ; + %load/vec4 v0x55cf9dc31a10_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_111.3, 8; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x55cf9dc31b70_0, 0; +T_111.3 ; + %jmp T_111; + .thread T_111; +# The file index is used to find the file name in the following table. +:file_names 38; + "N/A"; + ""; + "TC_Universe.v"; + "./ECP8e.v"; + "ECP8_components/ALU.v"; + "builtin_components/TC_Add.v"; + "builtin_components/TC_And.v"; + "builtin_components/TC_Ashr.v"; + "builtin_components/TC_Constant.v"; + "builtin_components/TC_Decoder3.v"; + "builtin_components/TC_Mul.v"; + "builtin_components/TC_Nand.v"; + "builtin_components/TC_Neg.v"; + "builtin_components/TC_Nor.v"; + "builtin_components/TC_Not.v"; + "builtin_components/TC_Or.v"; + "builtin_components/TC_Switch.v"; + "builtin_components/TC_Rol.v"; + "builtin_components/TC_Ror.v"; + "builtin_components/TC_Shl.v"; + "builtin_components/TC_Shr.v"; + "builtin_components/TC_Splitter8.v"; + "builtin_components/TC_Xnor.v"; + "builtin_components/TC_Xor.v"; + "builtin_components/TC_Buffer.v"; + "ECP8_components/subsys/COND.v"; + "builtin_components/TC_Counter.v"; + "ECP8_components/subsys/DEC.v"; + "builtin_components/TC_Decoder2.v"; + "builtin_components/TC_Halt.v"; + "builtin_components/TC_IOSwitch.v"; + "builtin_components/TC_Maker16.v"; + "builtin_components/TC_Or3.v"; + "builtin_components/TC_Program8_1.v"; + "builtin_components/TC_Ram.v"; + "ECP8_components/RegisterPlus.v"; + "builtin_components/TC_Register.v"; + "builtin_components/TC_Splitter16.v"; diff --git a/src/verilog/TC_Universe.v b/src/verilog/TC_Universe.v new file mode 100644 index 0000000..f3dff26 --- /dev/null +++ b/src/verilog/TC_Universe.v @@ -0,0 +1,71 @@ +`timescale 10ns / 1ns + +module TC_Universe (); + // clock and reset signals + reg clk; + reg rst; + + // test data + reg [15:0] index; + reg [7:0] mem [0:65535]; + reg [1024*4:0] file_name; + + integer i; + integer fd; + + // dut (Design Under Test) io + reg load; + reg save; + wire control_in; + reg [7:0] data_in; + wire control_out; + wire [7:0] data_out; + + // dut instantiation + ECP8e dut (.clk(clk), .rst(rst), + .arch_output_enable(control_out), .arch_output_value(data_out), + .arch_input_enable(control_in), .arch_input_value(data_in)); + + // generate clock + initial begin + clk = 1'b0; + forever #1 clk = ~clk; + end + + // generate reset + initial begin + rst = 1'b1; + #5 + rst = 1'b0; + end + + initial begin + assign data_in = 0; + + i = ($value$plusargs("INPUT_FILE=%s", file_name)); + if (i != 0) begin + i = 0; + fd = $fopen(file_name, "r"); + while (i < 65535 && !$feof(fd)) begin + mem[i] = $fgetc(fd); + end + end + end + + always @ (posedge control_in) begin + if (!rst) begin + data_in <= mem[index]; + index <= index + 1; + end + end + + always @ (negedge clk) begin + if (control_out && !rst) begin + //i = $fputc(data_out, 32'h8000_0001); + $display("received char 0x%h", data_out); + end + if (!control_in) begin + data_in <= 0; + end + end +endmodule diff --git a/src/verilog/build-ECP8e-iverilog.sh b/src/verilog/build-ECP8e-iverilog.sh new file mode 100755 index 0000000..7301dd7 --- /dev/null +++ b/src/verilog/build-ECP8e-iverilog.sh @@ -0,0 +1,3 @@ +#!/usr/bin/env bash +set -e +iverilog TC_Universe.v -o TC_Universe-iv.out -y builtin_components -y . -y "ECP8_components" -y "ECP8_components/subsys" "$@" diff --git a/src/verilog/builtin_components/TC_Add.v b/src/verilog/builtin_components/TC_Add.v new file mode 100644 index 0000000..c6ce6a5 --- /dev/null +++ b/src/verilog/builtin_components/TC_Add.v @@ -0,0 +1,12 @@ +module TC_Add (in0, in1, ci, out, co); + parameter UUID = 0; + parameter NAME = ""; + parameter BIT_WIDTH = 1; + input [BIT_WIDTH-1:0] in0; + input [BIT_WIDTH-1:0] in1; + input ci; + output [BIT_WIDTH-1:0] out; + output co; + + assign {co, out} = in0 + in1 + ci; +endmodule diff --git a/src/verilog/builtin_components/TC_And.v b/src/verilog/builtin_components/TC_And.v new file mode 100644 index 0000000..6d617b8 --- /dev/null +++ b/src/verilog/builtin_components/TC_And.v @@ -0,0 +1,10 @@ +module TC_And(in0, in1, out); + parameter UUID = 0; + parameter NAME = ""; + parameter BIT_WIDTH = 1; + input [BIT_WIDTH-1:0] in0; + input [BIT_WIDTH-1:0] in1; + output [BIT_WIDTH-1:0] out; + + assign out = in0 & in1; +endmodule diff --git a/src/verilog/builtin_components/TC_Ashr.v b/src/verilog/builtin_components/TC_Ashr.v new file mode 100644 index 0000000..b08f313 --- /dev/null +++ b/src/verilog/builtin_components/TC_Ashr.v @@ -0,0 +1,10 @@ +module TC_Ashr (in, shift, out); + parameter UUID = 0; + parameter NAME = ""; + parameter BIT_WIDTH = 1; + input [BIT_WIDTH-1:0] in; + input [7:0] shift; + output [BIT_WIDTH-1:0] out; + + assign out = in >>> shift; +endmodule diff --git a/src/verilog/builtin_components/TC_Buffer.v b/src/verilog/builtin_components/TC_Buffer.v new file mode 100644 index 0000000..1767646 --- /dev/null +++ b/src/verilog/builtin_components/TC_Buffer.v @@ -0,0 +1,9 @@ +module TC_Buffer(in, out); + parameter UUID = 0; + parameter NAME = ""; + parameter BIT_WIDTH = 1; + input [BIT_WIDTH-1:0] in; + output [BIT_WIDTH-1:0] out; + + assign out = in; +endmodule diff --git a/src/verilog/builtin_components/TC_Constant.v b/src/verilog/builtin_components/TC_Constant.v new file mode 100644 index 0000000..77eed10 --- /dev/null +++ b/src/verilog/builtin_components/TC_Constant.v @@ -0,0 +1,10 @@ + +module TC_Constant(out); + parameter UUID = 0; + parameter NAME = ""; + parameter BIT_WIDTH = 1; + parameter value = {BIT_WIDTH{1'b0}}; + output [BIT_WIDTH-1:0] out; + + assign out = value; +endmodule diff --git a/src/verilog/builtin_components/TC_Counter.v b/src/verilog/builtin_components/TC_Counter.v new file mode 100644 index 0000000..3deb861 --- /dev/null +++ b/src/verilog/builtin_components/TC_Counter.v @@ -0,0 +1,33 @@ +module TC_Counter (clk, rst, save, in, out); + parameter UUID = 0; + parameter NAME = ""; + parameter BIT_WIDTH = 8; + parameter count = 1; + input clk; + input rst; + input save; + input [BIT_WIDTH-1:0] in; + output reg [BIT_WIDTH-1:0] out; + + reg [BIT_WIDTH-1:0] value; + + initial begin + out = {BIT_WIDTH{1'b0}}; + value = {BIT_WIDTH{1'b0}}; + end + + always @ (posedge clk) begin + if (rst) begin + out <= {BIT_WIDTH{1'b0}}; + value <= {BIT_WIDTH{1'b0}}; + end else begin + if (save) begin + out <= in; + value <= in + count; + end else begin + out <= value; + value <= value + count; + end + end + end +endmodule diff --git a/src/verilog/builtin_components/TC_Decoder2.v b/src/verilog/builtin_components/TC_Decoder2.v new file mode 100644 index 0000000..07f571f --- /dev/null +++ b/src/verilog/builtin_components/TC_Decoder2.v @@ -0,0 +1,19 @@ +module TC_Decoder2 (sel0, sel1, out0, out1, out2, out3); + parameter UUID = 0; + parameter NAME = ""; + input sel0; + input sel1; + output reg out0; + output reg out1; + output reg out2; + output reg out3; + + always @ (sel1, sel0) begin + case({sel1, sel0}) + 2'b00 : {out3, out2, out1, out0} = 4'b0001; + 2'b01 : {out3, out2, out1, out0} = 4'b0010; + 2'b10 : {out3, out2, out1, out0} = 4'b0100; + 2'b11 : {out3, out2, out1, out0} = 4'b1000; + endcase + end +endmodule diff --git a/src/verilog/builtin_components/TC_Decoder3.v b/src/verilog/builtin_components/TC_Decoder3.v new file mode 100644 index 0000000..05f0980 --- /dev/null +++ b/src/verilog/builtin_components/TC_Decoder3.v @@ -0,0 +1,31 @@ +module TC_Decoder3 (dis, sel0, sel1, sel2, out0, out1, out2, out3, out4, out5, out6, out7); + parameter UUID = 0; + parameter NAME = ""; + input dis; + input sel0; + input sel1; + input sel2; + output reg out0; + output reg out1; + output reg out2; + output reg out3; + output reg out4; + output reg out5; + output reg out6; + output reg out7; + + always @ (dis or sel2 or sel1 or sel0) + begin + case({dis, sel2, sel1, sel0}) + 4'b0000 : {out7, out6, out5, out4, out3, out2, out1, out0} = 8'b0000_0001; + 4'b0001 : {out7, out6, out5, out4, out3, out2, out1, out0} = 8'b0000_0010; + 4'b0010 : {out7, out6, out5, out4, out3, out2, out1, out0} = 8'b0000_0100; + 4'b0011 : {out7, out6, out5, out4, out3, out2, out1, out0} = 8'b0000_1000; + 4'b0100 : {out7, out6, out5, out4, out3, out2, out1, out0} = 8'b0001_0000; + 4'b0101 : {out7, out6, out5, out4, out3, out2, out1, out0} = 8'b0010_0000; + 4'b0110 : {out7, out6, out5, out4, out3, out2, out1, out0} = 8'b0100_0000; + 4'b0111 : {out7, out6, out5, out4, out3, out2, out1, out0} = 8'b1000_0000; + default : {out7, out6, out5, out4, out3, out2, out1, out0} = 8'b0000_0000; + endcase + end +endmodule diff --git a/src/verilog/builtin_components/TC_Halt.v b/src/verilog/builtin_components/TC_Halt.v new file mode 100644 index 0000000..0b725c2 --- /dev/null +++ b/src/verilog/builtin_components/TC_Halt.v @@ -0,0 +1,15 @@ +module TC_Halt (clk, rst, en); + parameter UUID = 0; + parameter NAME = ""; + parameter HALT_MESSAGE = ""; + input clk; + input rst; + input en; + + always @ (negedge clk) begin + if (en) begin + $display("%s", HALT_MESSAGE); + $stop; + end + end +endmodule diff --git a/src/verilog/builtin_components/TC_IOSwitch.v b/src/verilog/builtin_components/TC_IOSwitch.v new file mode 100644 index 0000000..8317355 --- /dev/null +++ b/src/verilog/builtin_components/TC_IOSwitch.v @@ -0,0 +1,17 @@ +module TC_IOSwitch (in, en, out); + parameter UUID = 0; + parameter NAME = ""; + parameter BIT_WIDTH = 1; + input en; + input [BIT_WIDTH-1:0] in; + output [BIT_WIDTH-1:0] out; + reg [BIT_WIDTH-1:0] outval; + + always @ (en or in) begin + case(en) + 1'b0 : outval = {BIT_WIDTH{1'b0}}; + 1'b1 : outval = in; + endcase + end + assign out = outval; +endmodule diff --git a/src/verilog/builtin_components/TC_Maker16.v b/src/verilog/builtin_components/TC_Maker16.v new file mode 100644 index 0000000..deb770d --- /dev/null +++ b/src/verilog/builtin_components/TC_Maker16.v @@ -0,0 +1,9 @@ +module TC_Maker16 (in0, in1, out); + parameter UUID = 0; + parameter NAME = ""; + input [7:0] in0; + input [7:0] in1; + output [15:0] out; + + assign out = {in1, in0}; +endmodule diff --git a/src/verilog/builtin_components/TC_Mul.v b/src/verilog/builtin_components/TC_Mul.v new file mode 100644 index 0000000..977932a --- /dev/null +++ b/src/verilog/builtin_components/TC_Mul.v @@ -0,0 +1,12 @@ +module TC_Mul (in0, in1, out0, out1); + parameter UUID = 0; + parameter NAME = ""; + parameter BIT_WIDTH = 1; + input [BIT_WIDTH-1:0] in0; + input [BIT_WIDTH-1:0] in1; + output [BIT_WIDTH-1:0] out0; + output [BIT_WIDTH-1:0] out1; + + assign out0 = in0 / in1; + assign out1 = in0 % in1; +endmodule diff --git a/src/verilog/builtin_components/TC_Nand.v b/src/verilog/builtin_components/TC_Nand.v new file mode 100644 index 0000000..65a4d11 --- /dev/null +++ b/src/verilog/builtin_components/TC_Nand.v @@ -0,0 +1,10 @@ +module TC_Nand(in0, in1, out); + parameter UUID = 0; + parameter NAME = ""; + parameter BIT_WIDTH = 1; + input [BIT_WIDTH-1:0] in0; + input [BIT_WIDTH-1:0] in1; + output [BIT_WIDTH-1:0] out; + + assign out = ~(in0 & in1); +endmodule diff --git a/src/verilog/builtin_components/TC_Neg.v b/src/verilog/builtin_components/TC_Neg.v new file mode 100644 index 0000000..9781da1 --- /dev/null +++ b/src/verilog/builtin_components/TC_Neg.v @@ -0,0 +1,9 @@ +module TC_Neg (in, out); + parameter UUID = 0; + parameter NAME = ""; + parameter BIT_WIDTH = 1; + input [BIT_WIDTH-1:0] in; + output [BIT_WIDTH-1:0] out; + + assign out = {BIT_WIDTH{1'b0}} - in; +endmodule diff --git a/src/verilog/builtin_components/TC_Nor.v b/src/verilog/builtin_components/TC_Nor.v new file mode 100644 index 0000000..98872ca --- /dev/null +++ b/src/verilog/builtin_components/TC_Nor.v @@ -0,0 +1,10 @@ +module TC_Nor(in0, in1, out); + parameter UUID = 0; + parameter NAME = ""; + parameter BIT_WIDTH = 1; + input [BIT_WIDTH-1:0] in0; + input [BIT_WIDTH-1:0] in1; + output [BIT_WIDTH-1:0] out; + + assign out = ~(in0 | in1); +endmodule diff --git a/src/verilog/builtin_components/TC_Not.v b/src/verilog/builtin_components/TC_Not.v new file mode 100644 index 0000000..78e931a --- /dev/null +++ b/src/verilog/builtin_components/TC_Not.v @@ -0,0 +1,9 @@ +module TC_Not(in, out); + parameter UUID = 0; + parameter NAME = ""; + parameter BIT_WIDTH = 1; + input [BIT_WIDTH-1:0] in; + output [BIT_WIDTH-1:0] out; + + assign out = ~in; +endmodule diff --git a/src/verilog/builtin_components/TC_Or.v b/src/verilog/builtin_components/TC_Or.v new file mode 100644 index 0000000..6dd893e --- /dev/null +++ b/src/verilog/builtin_components/TC_Or.v @@ -0,0 +1,10 @@ +module TC_Or(in0, in1, out); + parameter UUID = 0; + parameter NAME = ""; + parameter BIT_WIDTH = 1; + input [BIT_WIDTH-1:0] in0; + input [BIT_WIDTH-1:0] in1; + output [BIT_WIDTH-1:0] out; + + assign out = in0 | in1; +endmodule diff --git a/src/verilog/builtin_components/TC_Or3.v b/src/verilog/builtin_components/TC_Or3.v new file mode 100644 index 0000000..818a8ea --- /dev/null +++ b/src/verilog/builtin_components/TC_Or3.v @@ -0,0 +1,11 @@ +module TC_Or3(in0, in1, in2, out); + parameter UUID = 0; + parameter NAME = ""; + parameter BIT_WIDTH = 1; + input [BIT_WIDTH-1:0] in0; + input [BIT_WIDTH-1:0] in1; + input [BIT_WIDTH-1:0] in2; + output [BIT_WIDTH-1:0] out; + + assign out = in0 | in1 | in2; +endmodule diff --git a/src/verilog/builtin_components/TC_Program8_1.v b/src/verilog/builtin_components/TC_Program8_1.v new file mode 100644 index 0000000..7e5db5d --- /dev/null +++ b/src/verilog/builtin_components/TC_Program8_1.v @@ -0,0 +1,46 @@ +module TC_Program8_1 (clk, rst, address, out); + parameter UUID = 0; + parameter NAME = ""; + parameter MAX_WORD_COUNT = 256; + parameter DEFAULT_FILE_NAME = "test_jumps.mem"; + parameter ARG_SIG = "FILE_NAME=%s"; + reg [1024*8:0] hexfile; + input clk; + input rst; + input [7:0] address; + output reg [7:0] out; + + //reg [7:0] mem [0:BIT_DMAX_WORD_COUNTEPTH]; + reg [7:0] mem [0:MAX_WORD_COUNT - 1]; + + integer fd; + integer i; + + initial begin + hexfile = DEFAULT_FILE_NAME; + $display("param %0s", hexfile); + i = ($value$plusargs(ARG_SIG, hexfile)); + $display("loading %0s", hexfile); + fd = $fopen(hexfile, "r"); + if (fd) begin + i = 0; + while (!$feof(fd) && i < MAX_WORD_COUNT) begin + mem[i] = $fgetc(fd); + i = i + 1; + end + $display("read %0d bytes", i); + end else begin + $display("file not found"); + end + $fclose(fd); + out = 8'b0000_0000; + end + + always @ (address or rst) begin + if (rst) begin + out = 8'b0000_0000; + end else begin + out = mem[address]; + end + end +endmodule diff --git a/src/verilog/builtin_components/TC_Ram.v b/src/verilog/builtin_components/TC_Ram.v new file mode 100644 index 0000000..60b19ad --- /dev/null +++ b/src/verilog/builtin_components/TC_Ram.v @@ -0,0 +1,110 @@ +module TC_Ram (clk, rst, load, save, address, in0, in1, in2, in3, out0, out1, out2, out3); + parameter UUID = 0; + parameter NAME = ""; + parameter WORD_WIDTH = 256; + parameter WORD_COUNT = 256; + input clk; + input rst; + input load; + input save; + input [31:0] address; + input [63:0] in0; + input [63:0] in1; + input [63:0] in2; + input [63:0] in3; + output reg [63:0] out0; + output reg [63:0] out1; + output reg [63:0] out2; + output reg [63:0] out3; + + reg [WORD_WIDTH-1:0] mem [0:WORD_COUNT]; + + integer i; + + initial begin + for (i=0; i> shift) | (in << (BIT_WIDTH - shift)); +endmodule diff --git a/src/verilog/builtin_components/TC_Ror.v b/src/verilog/builtin_components/TC_Ror.v new file mode 100644 index 0000000..6adba08 --- /dev/null +++ b/src/verilog/builtin_components/TC_Ror.v @@ -0,0 +1,10 @@ +module TC_Ror (in, shift, out); + parameter UUID = 0; + parameter NAME = ""; + parameter BIT_WIDTH = 8; + input [BIT_WIDTH-1:0] in; + input [7:0] shift; + output [BIT_WIDTH-1:0] out; + + assign out = (in << shift) | (in >> (BIT_WIDTH - shift)); +endmodule diff --git a/src/verilog/builtin_components/TC_Shl.v b/src/verilog/builtin_components/TC_Shl.v new file mode 100644 index 0000000..9050e0e --- /dev/null +++ b/src/verilog/builtin_components/TC_Shl.v @@ -0,0 +1,10 @@ +module TC_Shl (in, shift, out); + parameter UUID = 0; + parameter NAME = ""; + parameter BIT_WIDTH = 1; + input [BIT_WIDTH-1:0] in; + input [7:0] shift; + output [BIT_WIDTH-1:0] out; + + assign out = in << shift; +endmodule diff --git a/src/verilog/builtin_components/TC_Shr.v b/src/verilog/builtin_components/TC_Shr.v new file mode 100644 index 0000000..56a340b --- /dev/null +++ b/src/verilog/builtin_components/TC_Shr.v @@ -0,0 +1,10 @@ +module TC_Shr (in, shift, out); + parameter UUID = 0; + parameter NAME = ""; + parameter BIT_WIDTH = 1; + input [BIT_WIDTH-1:0] in; + input [7:0] shift; + output [BIT_WIDTH-1:0] out; + + assign out = in >> shift; +endmodule diff --git a/src/verilog/builtin_components/TC_Splitter16.v b/src/verilog/builtin_components/TC_Splitter16.v new file mode 100644 index 0000000..7afae32 --- /dev/null +++ b/src/verilog/builtin_components/TC_Splitter16.v @@ -0,0 +1,9 @@ +module TC_Splitter16 (in, out0, out1); + parameter UUID = 0; + parameter NAME = ""; + input [15:0] in; + output [7:0] out0; + output [7:0] out1; + + assign {out1, out0} = in; +endmodule diff --git a/src/verilog/builtin_components/TC_Splitter8.v b/src/verilog/builtin_components/TC_Splitter8.v new file mode 100644 index 0000000..192841b --- /dev/null +++ b/src/verilog/builtin_components/TC_Splitter8.v @@ -0,0 +1,15 @@ +module TC_Splitter8 (in, out0, out1, out2, out3, out4, out5, out6, out7); + parameter UUID = 0; + parameter NAME = ""; + input [7:0] in; + output out0; + output out1; + output out2; + output out3; + output out4; + output out5; + output out6; + output out7; + + assign {out7, out6, out5, out4, out3, out2, out1, out0} = in; +endmodule diff --git a/src/verilog/builtin_components/TC_Switch.v b/src/verilog/builtin_components/TC_Switch.v new file mode 100644 index 0000000..7dc273f --- /dev/null +++ b/src/verilog/builtin_components/TC_Switch.v @@ -0,0 +1,17 @@ +module TC_Switch(en, in, out); + parameter UUID = 0; + parameter NAME = ""; + parameter BIT_WIDTH = 1; + input en; + input [BIT_WIDTH-1:0] in; + output [BIT_WIDTH-1:0] out; + reg [BIT_WIDTH-1:0] outval; + + always @ (en or in) begin + case(en) + 1'b0 : outval = {BIT_WIDTH{1'b0}}; + 1'b1 : outval = in; + endcase + end + assign out = outval; +endmodule diff --git a/src/verilog/builtin_components/TC_Xnor.v b/src/verilog/builtin_components/TC_Xnor.v new file mode 100644 index 0000000..d5761b2 --- /dev/null +++ b/src/verilog/builtin_components/TC_Xnor.v @@ -0,0 +1,10 @@ +module TC_Xnor(in0, in1, out); + parameter UUID = 0; + parameter NAME = ""; + parameter BIT_WIDTH = 1; + input [BIT_WIDTH-1:0] in0; + input [BIT_WIDTH-1:0] in1; + output [BIT_WIDTH-1:0] out; + + assign out = in0 ~^ in1; +endmodule diff --git a/src/verilog/builtin_components/TC_Xor.v b/src/verilog/builtin_components/TC_Xor.v new file mode 100644 index 0000000..ee8ee16 --- /dev/null +++ b/src/verilog/builtin_components/TC_Xor.v @@ -0,0 +1,10 @@ +module TC_Xor(in0, in1, out); + parameter UUID = 0; + parameter NAME = ""; + parameter BIT_WIDTH = 1; + input [BIT_WIDTH-1:0] in0; + input [BIT_WIDTH-1:0] in1; + output [BIT_WIDTH-1:0] out; + + assign out = in0 ^ in1; +endmodule