commit dc905691d94fd831cd7db5c982bffd9c99337afe
Author: Elaina Claus <elaina.claus@chtm.me>
Date:   Thu Jul 27 07:54:43 2023 -0400

    add program and cpu opcode defs added

diff --git a/add.asm b/add.asm
new file mode 100644
index 0000000..7d9dc40
--- /dev/null
+++ b/add.asm
@@ -0,0 +1,26 @@
+#include "definitions.asm"
+; program adds 5 to the input and puts
+; the sum on the output, no carry
+prog:
+    imm6 0            ; start at 0
+    load r0, r1
+    imm6 prog.add    ; load address to add5 and branch
+    ba
+.add:    
+    imm6 0x01           ; edit this imm value to change count-by value
+    load r0, r2
+    add                 ; r1 + 0x05 = r3
+    load r3, r4         ; save result in r4
+    load r3, r2         
+    imm6 0x32
+    load r0, r1
+    sub                 ; 50 - result = r3
+    imm6 prog.result
+    beqz                ; PC = R0 if R3 = 0
+    load r4, r1         ; add5(result)
+    imm6 prog.add
+    ba
+.result:
+    out r4
+.hcf:
+    hcf
\ No newline at end of file
diff --git a/definitions.asm b/definitions.asm
new file mode 100644
index 0000000..148cbc5
--- /dev/null
+++ b/definitions.asm
@@ -0,0 +1,64 @@
+; see https://github.com/hlorenzi/customasm for documentation
+
+#bankdef program
+{
+    #bits 8
+    #addr 0x00
+    #size 0xFF
+    #outp 0x00
+}
+#subruledef register
+{
+    0      => 0b000
+    1      => 0b001
+    2      => 0b010
+    3      => 0b011
+    4      => 0b100
+    5      => 0b101
+    RES => 0b111
+}
+
+#ruledef
+{
+    imm6 {value}                            => 0b00 @ value`6
+    load r{src: register}, r{dst: register} => 0b10 @ src`3 @ dst`3
+    in r{r: register}                            => 0b10 @ 0b110 @ r
+    out r{r: register}                           => 0b10 @ r @ 0b110
+}    
+
+#ruledef
+{
+    or          => 0b01 @ 0b000 @ 0b000
+    nand        => 0b01 @ 0b000 @ 0b001
+    nor         => 0b01 @ 0b000 @ 0b010
+    and         => 0b01 @ 0b000 @ 0b011
+    add         => 0b01 @ 0b000 @ 0b100
+    sub         => 0b01 @ 0b000 @ 0b101
+    ALU_RES1    => 0b01 @ 0b000 @ 0b110
+    ALU_RES2    => 0b01 @ 0b000 @ 0b111
+    ALU_EXT1_RES1 => 0b01 @ 0b001 @ 0b000
+    ALU_EXT1_RES2 => 0b01 @ 0b001 @ 0b001
+    ALU_EXT1_RES3 => 0b01 @ 0b001 @ 0b010
+    ALU_EXT1_RES4 => 0b01 @ 0b001 @ 0b011
+    ALU_EXT1_RES5 => 0b01 @ 0b001 @ 0b100
+    ALU_EXT1_RES6 => 0b01 @ 0b001 @ 0b101
+    ALU_EXT1_RES7 => 0b01 @ 0b001 @ 0b110
+    ALU_EXT1_RES8 => 0b01 @ 0b001 @ 0b111
+}
+
+#ruledef
+{
+    bn => 0b11 @ 0b000 @ 0b000
+    beqz => 0b11 @ 0b000 @ 0b001
+    bltz => 0b11 @ 0b000 @ 0b010
+    blez => 0b11 @ 0b000 @ 0b011
+    ba => 0b11 @ 0b000 @ 0b100
+    bnez => 0b11 @ 0b000 @ 0b101
+    bgez => 0b11 @ 0b000 @ 0b110
+    bgtz => 0b11 @ 0b000 @ 0b111
+}
+
+#ruledef
+{
+    hcf => 0b10 @ 0b111 @ 0b111
+}