47 lines
1.2 KiB
Verilog
47 lines
1.2 KiB
Verilog
module TC_Program8_1 (clk, rst, address, out);
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parameter UUID = 0;
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parameter NAME = "";
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parameter MAX_WORD_COUNT = 256;
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parameter DEFAULT_FILE_NAME = "test_jumps.mem";
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parameter ARG_SIG = "FILE_NAME=%s";
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reg [1024*8:0] hexfile;
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input clk;
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input rst;
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input [7:0] address;
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output reg [7:0] out;
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//reg [7:0] mem [0:BIT_DMAX_WORD_COUNTEPTH];
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reg [7:0] mem [0:MAX_WORD_COUNT - 1];
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integer fd;
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integer i;
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initial begin
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hexfile = DEFAULT_FILE_NAME;
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$display("param %0s", hexfile);
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i = ($value$plusargs(ARG_SIG, hexfile));
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$display("loading %0s", hexfile);
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fd = $fopen(hexfile, "r");
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if (fd) begin
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i = 0;
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while (!$feof(fd) && i < MAX_WORD_COUNT) begin
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mem[i] = $fgetc(fd);
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i = i + 1;
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end
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$display("read %0d bytes", i);
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end else begin
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$display("file not found");
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end
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$fclose(fd);
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out = 8'b0000_0000;
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end
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always @ (address or rst) begin
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if (rst) begin
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out = 8'b0000_0000;
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end else begin
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out = mem[address];
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end
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end
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endmodule
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