rename add5
This commit is contained in:
50
add.asm
50
add.asm
@@ -1,26 +1,26 @@
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#include "definitions.asm"
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; program adds 5 to the input and puts
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; the sum on the output, no carry
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prog:
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imm6 0 ; start at 0
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load r0, r1
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imm6 prog.add ; load address to add5 and branch
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ba
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.add:
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imm6 0x01 ; edit this imm value to change count-by value
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load r0, r2
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add ; r1 + 0x05 = r3
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load r3, r4 ; save result in r4
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load r3, r2
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imm6 0x32
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load r0, r1
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sub ; 50 - result = r3
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imm6 prog.result
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beqz ; PC = R0 if R3 = 0
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load r4, r1 ; add5(result)
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imm6 prog.add
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ba
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.result:
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out r4
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.hcf:
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#include "definitions.asm"
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; program adds 5 to the input and puts
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; the sum on the output, no carry
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prog:
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imm6 0 ; start at 0
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load r0, r1
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imm6 prog.add ; load address to add5 and branch
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ba
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.add:
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imm6 0x01 ; edit this imm value to change count-by value
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load r0, r2
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add ; r1 + 0x05 = r3
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load r3, r4 ; save result in r4
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load r3, r2
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imm6 0x32
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load r0, r1
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sub ; 50 - result = r3
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imm6 prog.result
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beqz ; PC = R0 if R3 = 0
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load r4, r1 ; add5(result)
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imm6 prog.add
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ba
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.result:
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out r4
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.hcf:
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hcf
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144
definitions.asm
144
definitions.asm
@@ -1,72 +1,72 @@
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; see https://github.com/hlorenzi/customasm for documentation
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#bankdef program
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{
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#bits 8
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#addr 0x00
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#size 0xFF
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#outp 0x00
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}
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#subruledef register
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{
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0 => 0b000
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1 => 0b001
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2 => 0b010
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3 => 0b011
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4 => 0b100
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5 => 0b101
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}
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#ruledef
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{
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imm6 {value} => 0b00 @ value`6
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load r{src: register}, r{dst: register} => 0b10 @ src`3 @ dst`3
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load [r3], r{dst: register} => 0b10 @ 0b110 @ dst`3
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load r{src: register}, [r3] => 0b10 @ src`3 @ 0b110
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aload => 0b10 @ 0b110 @ 0b110
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in r{r: register} => 0b10 @ 0b110 @ r
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out r{r: register} => 0b10 @ r @ 0b110
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}
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#ruledef
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{
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or => 0b01 @ 0b000 @ 0b000
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nand => 0b01 @ 0b000 @ 0b001
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nor => 0b01 @ 0b000 @ 0b010
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and => 0b01 @ 0b000 @ 0b011
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add => 0b01 @ 0b000 @ 0b100
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sub => 0b01 @ 0b000 @ 0b101
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ALU_RES1 => 0b01 @ 0b000 @ 0b110
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ALU_RES2 => 0b01 @ 0b000 @ 0b111
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ALU_EXT1_RES0 => 0b01 @ 0b001 @ 0b000
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ALU_EXT1_RES1 => 0b01 @ 0b001 @ 0b001
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ALU_EXT1_RES2 => 0b01 @ 0b001 @ 0b010
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ALU_EXT1_RES3 => 0b01 @ 0b001 @ 0b011
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ALU_EXT1_RES4 => 0b01 @ 0b001 @ 0b100
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ALU_EXT1_RES5 => 0b01 @ 0b001 @ 0b101
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ALU_EXT1_RES6 => 0b01 @ 0b001 @ 0b110
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ALU_EXT1_RES7 => 0b01 @ 0b001 @ 0b111
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; and so on...
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ALU_EXT7_RES1 => 0b01 @ 0b111 @ 0b000
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}
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; conditional jump block
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#ruledef
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{
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bn => 0b11 @ 0b000 @ 0b000
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beqz => 0b11 @ 0b000 @ 0b001
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bltz => 0b11 @ 0b000 @ 0b010
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blez => 0b11 @ 0b000 @ 0b011
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ba => 0b11 @ 0b000 @ 0b100
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bnez => 0b11 @ 0b000 @ 0b101
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bgez => 0b11 @ 0b000 @ 0b110
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bgtz => 0b11 @ 0b000 @ 0b111
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}
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; halt encodings
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#ruledef
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{
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hcf => 0b10 @ 0b111 @ 0b111
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halt => 0b10 @ 0b111 @ 0b111
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}
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; see https://github.com/hlorenzi/customasm for documentation
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#bankdef program
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{
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#bits 8
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#addr 0x00
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#size 0xFF
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#outp 0x00
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}
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#subruledef register
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{
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0 => 0b000
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1 => 0b001
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2 => 0b010
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3 => 0b011
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4 => 0b100
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5 => 0b101
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}
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#ruledef
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{
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imm6 {value} => 0b00 @ value`6
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load r{src: register}, r{dst: register} => 0b10 @ src`3 @ dst`3
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load [r3], r{dst: register} => 0b10 @ 0b110 @ dst`3
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load r{src: register}, [r3] => 0b10 @ src`3 @ 0b110
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aload => 0b10 @ 0b110 @ 0b110
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in r{r: register} => 0b10 @ 0b110 @ r
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out r{r: register} => 0b10 @ r @ 0b110
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}
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#ruledef
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{
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or => 0b01 @ 0b000 @ 0b000
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nand => 0b01 @ 0b000 @ 0b001
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nor => 0b01 @ 0b000 @ 0b010
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and => 0b01 @ 0b000 @ 0b011
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add => 0b01 @ 0b000 @ 0b100
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sub => 0b01 @ 0b000 @ 0b101
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ALU_RES1 => 0b01 @ 0b000 @ 0b110
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ALU_RES2 => 0b01 @ 0b000 @ 0b111
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ALU_EXT1_RES0 => 0b01 @ 0b001 @ 0b000
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ALU_EXT1_RES1 => 0b01 @ 0b001 @ 0b001
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ALU_EXT1_RES2 => 0b01 @ 0b001 @ 0b010
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ALU_EXT1_RES3 => 0b01 @ 0b001 @ 0b011
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ALU_EXT1_RES4 => 0b01 @ 0b001 @ 0b100
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ALU_EXT1_RES5 => 0b01 @ 0b001 @ 0b101
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ALU_EXT1_RES6 => 0b01 @ 0b001 @ 0b110
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ALU_EXT1_RES7 => 0b01 @ 0b001 @ 0b111
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; and so on...
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ALU_EXT7_RES1 => 0b01 @ 0b111 @ 0b000
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}
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; conditional jump block
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#ruledef
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{
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bn => 0b11 @ 0b000 @ 0b000
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beqz => 0b11 @ 0b000 @ 0b001
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bltz => 0b11 @ 0b000 @ 0b010
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blez => 0b11 @ 0b000 @ 0b011
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ba => 0b11 @ 0b000 @ 0b100
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bnez => 0b11 @ 0b000 @ 0b101
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bgez => 0b11 @ 0b000 @ 0b110
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bgtz => 0b11 @ 0b000 @ 0b111
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}
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; halt encodings
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#ruledef
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{
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hcf => 0b10 @ 0b111 @ 0b111
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halt => 0b10 @ 0b111 @ 0b111
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}
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