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rename add5

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This commit is contained in:
Elaina Claus
2023-07-27 18:23:25 -04:00
parent 053cd0bf3f
commit cf765b7422
2 changed files with 97 additions and 97 deletions
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50
add.asm
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@@ -1,26 +1,26 @@
#include "definitions.asm" #include "definitions.asm"
; program adds 5 to the input and puts ; program adds 5 to the input and puts
; the sum on the output, no carry ; the sum on the output, no carry
prog: prog:
imm6 0 ; start at 0 imm6 0 ; start at 0
load r0, r1 load r0, r1
imm6 prog.add ; load address to add5 and branch imm6 prog.add ; load address to add5 and branch
ba ba
.add: .add:
imm6 0x01 ; edit this imm value to change count-by value imm6 0x01 ; edit this imm value to change count-by value
load r0, r2 load r0, r2
add ; r1 + 0x05 = r3 add ; r1 + 0x05 = r3
load r3, r4 ; save result in r4 load r3, r4 ; save result in r4
load r3, r2 load r3, r2
imm6 0x32 imm6 0x32
load r0, r1 load r0, r1
sub ; 50 - result = r3 sub ; 50 - result = r3
imm6 prog.result imm6 prog.result
beqz ; PC = R0 if R3 = 0 beqz ; PC = R0 if R3 = 0
load r4, r1 ; add5(result) load r4, r1 ; add5(result)
imm6 prog.add imm6 prog.add
ba ba
.result: .result:
out r4 out r4
.hcf: .hcf:
hcf hcf

144
definitions.asm
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@@ -1,72 +1,72 @@
; see https://github.com/hlorenzi/customasm for documentation ; see https://github.com/hlorenzi/customasm for documentation
#bankdef program #bankdef program
{ {
#bits 8 #bits 8
#addr 0x00 #addr 0x00
#size 0xFF #size 0xFF
#outp 0x00 #outp 0x00
} }
#subruledef register #subruledef register
{ {
0 => 0b000 0 => 0b000
1 => 0b001 1 => 0b001
2 => 0b010 2 => 0b010
3 => 0b011 3 => 0b011
4 => 0b100 4 => 0b100
5 => 0b101 5 => 0b101
} }
#ruledef #ruledef
{ {
imm6 {value} => 0b00 @ value`6 imm6 {value} => 0b00 @ value`6
load r{src: register}, r{dst: register} => 0b10 @ src`3 @ dst`3 load r{src: register}, r{dst: register} => 0b10 @ src`3 @ dst`3
load [r3], r{dst: register} => 0b10 @ 0b110 @ dst`3 load [r3], r{dst: register} => 0b10 @ 0b110 @ dst`3
load r{src: register}, [r3] => 0b10 @ src`3 @ 0b110 load r{src: register}, [r3] => 0b10 @ src`3 @ 0b110
aload => 0b10 @ 0b110 @ 0b110 aload => 0b10 @ 0b110 @ 0b110
in r{r: register} => 0b10 @ 0b110 @ r in r{r: register} => 0b10 @ 0b110 @ r
out r{r: register} => 0b10 @ r @ 0b110 out r{r: register} => 0b10 @ r @ 0b110
} }
#ruledef #ruledef
{ {
or => 0b01 @ 0b000 @ 0b000 or => 0b01 @ 0b000 @ 0b000
nand => 0b01 @ 0b000 @ 0b001 nand => 0b01 @ 0b000 @ 0b001
nor => 0b01 @ 0b000 @ 0b010 nor => 0b01 @ 0b000 @ 0b010
and => 0b01 @ 0b000 @ 0b011 and => 0b01 @ 0b000 @ 0b011
add => 0b01 @ 0b000 @ 0b100 add => 0b01 @ 0b000 @ 0b100
sub => 0b01 @ 0b000 @ 0b101 sub => 0b01 @ 0b000 @ 0b101
ALU_RES1 => 0b01 @ 0b000 @ 0b110 ALU_RES1 => 0b01 @ 0b000 @ 0b110
ALU_RES2 => 0b01 @ 0b000 @ 0b111 ALU_RES2 => 0b01 @ 0b000 @ 0b111
ALU_EXT1_RES0 => 0b01 @ 0b001 @ 0b000 ALU_EXT1_RES0 => 0b01 @ 0b001 @ 0b000
ALU_EXT1_RES1 => 0b01 @ 0b001 @ 0b001 ALU_EXT1_RES1 => 0b01 @ 0b001 @ 0b001
ALU_EXT1_RES2 => 0b01 @ 0b001 @ 0b010 ALU_EXT1_RES2 => 0b01 @ 0b001 @ 0b010
ALU_EXT1_RES3 => 0b01 @ 0b001 @ 0b011 ALU_EXT1_RES3 => 0b01 @ 0b001 @ 0b011
ALU_EXT1_RES4 => 0b01 @ 0b001 @ 0b100 ALU_EXT1_RES4 => 0b01 @ 0b001 @ 0b100
ALU_EXT1_RES5 => 0b01 @ 0b001 @ 0b101 ALU_EXT1_RES5 => 0b01 @ 0b001 @ 0b101
ALU_EXT1_RES6 => 0b01 @ 0b001 @ 0b110 ALU_EXT1_RES6 => 0b01 @ 0b001 @ 0b110
ALU_EXT1_RES7 => 0b01 @ 0b001 @ 0b111 ALU_EXT1_RES7 => 0b01 @ 0b001 @ 0b111
; and so on... ; and so on...
ALU_EXT7_RES1 => 0b01 @ 0b111 @ 0b000 ALU_EXT7_RES1 => 0b01 @ 0b111 @ 0b000
} }
; conditional jump block ; conditional jump block
#ruledef #ruledef
{ {
bn => 0b11 @ 0b000 @ 0b000 bn => 0b11 @ 0b000 @ 0b000
beqz => 0b11 @ 0b000 @ 0b001 beqz => 0b11 @ 0b000 @ 0b001
bltz => 0b11 @ 0b000 @ 0b010 bltz => 0b11 @ 0b000 @ 0b010
blez => 0b11 @ 0b000 @ 0b011 blez => 0b11 @ 0b000 @ 0b011
ba => 0b11 @ 0b000 @ 0b100 ba => 0b11 @ 0b000 @ 0b100
bnez => 0b11 @ 0b000 @ 0b101 bnez => 0b11 @ 0b000 @ 0b101
bgez => 0b11 @ 0b000 @ 0b110 bgez => 0b11 @ 0b000 @ 0b110
bgtz => 0b11 @ 0b000 @ 0b111 bgtz => 0b11 @ 0b000 @ 0b111
} }
; halt encodings ; halt encodings
#ruledef #ruledef
{ {
hcf => 0b10 @ 0b111 @ 0b111 hcf => 0b10 @ 0b111 @ 0b111
halt => 0b10 @ 0b111 @ 0b111 halt => 0b10 @ 0b111 @ 0b111
} }