raw verilog output from TC 'works' but the SoC seems to not work correctly.
This commit is contained in:
@@ -37,7 +37,6 @@
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3 => 0b011
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3 => 0b011
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4 => 0b100
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4 => 0b100
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5 => 0b101
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5 => 0b101
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}
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}
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; immediate load encodings
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; immediate load encodings
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@@ -51,8 +50,8 @@
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{
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{
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load r{src: register}, r{dst: register} => 0b10 @ src`3 @ dst`3
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load r{src: register}, r{dst: register} => 0b10 @ src`3 @ dst`3
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aload => 0b10 @ 0b110 @ 0b110
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aload => 0b10 @ 0b110 @ 0b110
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in r{r: register} => 0b10 @ 0b110 @ r
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in r{r: register} => 0b10 @ 0b110 @ r`3
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out r{r: register} => 0b10 @ r @ 0b110
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out r{r: register} => 0b10 @ r`3 @ 0b110
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}
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}
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; EXT0 functions
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; EXT0 functions
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8
src/microcode/misc/outport_test.asm
Normal file
8
src/microcode/misc/outport_test.asm
Normal file
@@ -0,0 +1,8 @@
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#include "../definitions.asm"
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#bank program
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prog:
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imm6 42
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.result:
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out r0
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halt
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@@ -1,8 +1,6 @@
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#include "definitions.asm"
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#include "definitions.asm"
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; just a quick scratch pad place for programs
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; template/scratch pad
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prog:
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prog:
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in r1
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imm6 0x1
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in r2
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xor
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.result:
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.result:
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out r3
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out r0
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221
src/verilog/ECP8_components/ALU.v
Normal file
221
src/verilog/ECP8_components/ALU.v
Normal file
@@ -0,0 +1,221 @@
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module ALU (clk, rst, Instruction, A, B, D_OUT_EN, D, CF, C);
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parameter UUID = 0;
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parameter NAME = "";
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input wire clk;
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input wire rst;
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input wire [7:0] Instruction;
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input wire [7:0] A;
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input wire [7:0] B;
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output wire [0:0] D_OUT_EN;
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output wire [7:0] D;
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output wire [0:0] CF;
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output wire [7:0] C;
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TC_Splitter8 # (.UUID(64'd1753460274403159300 ^ UUID)) Splitter8_0 (.in(wire_29), .out0(wire_7), .out1(wire_82), .out2(wire_55), .out3(wire_69), .out4(wire_42), .out5(wire_31), .out6(), .out7());
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TC_Decoder3 # (.UUID(64'd812012822489249482 ^ UUID)) Decoder3_1 (.dis(1'd0), .sel0(wire_7), .sel1(wire_82), .sel2(wire_55), .out0(wire_5), .out1(wire_1), .out2(wire_4), .out3(wire_16), .out4(wire_24), .out5(wire_0), .out6(wire_26), .out7(wire_48));
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TC_Add # (.UUID(64'd1656672475853897358 ^ UUID), .BIT_WIDTH(64'd8)) Add8_2 (.in0(wire_86), .in1(wire_45), .ci(1'd0), .out(wire_33), .co(wire_21));
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TC_Switch # (.UUID(64'd2854607076807969927 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_3 (.en(wire_24), .in(wire_2), .out(wire_72));
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TC_Switch # (.UUID(64'd1098925891083976806 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_4 (.en(wire_24), .in(wire_6), .out(wire_84));
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TC_Switch # (.UUID(64'd272865694635219578 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_5 (.en(wire_24), .in(wire_62), .out(wire_22_4));
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TC_Neg # (.UUID(64'd4234413084985973774 ^ UUID), .BIT_WIDTH(64'd8)) Neg8_6 (.in(wire_68), .out(wire_45));
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TC_Add # (.UUID(64'd2365866274018282956 ^ UUID), .BIT_WIDTH(64'd8)) Add8_7 (.in0(wire_84), .in1(wire_72), .ci(1'd0), .out(wire_62), .co(wire_23));
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TC_Switch # (.UUID(64'd2540442194520213284 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_8 (.en(wire_16), .in(wire_6), .out(wire_86));
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TC_Switch # (.UUID(64'd927777902762540353 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_9 (.en(wire_16), .in(wire_2), .out(wire_68));
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TC_Switch # (.UUID(64'd4324181735425917878 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_10 (.en(wire_16), .in(wire_33), .out(wire_22_2));
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TC_Switch # (.UUID(64'd1224106639434152846 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_11 (.en(wire_5), .in(wire_6), .out(wire_39));
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TC_Switch # (.UUID(64'd1322051027298697595 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_12 (.en(wire_5), .in(wire_2), .out(wire_60));
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TC_Switch # (.UUID(64'd4279546958457643910 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_13 (.en(wire_5), .in(wire_52), .out(wire_8_0));
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TC_Switch # (.UUID(64'd1407183183188242545 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_14 (.en(wire_1), .in(wire_2), .out(wire_66));
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TC_Switch # (.UUID(64'd825188955478831971 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_15 (.en(wire_1), .in(wire_6), .out(wire_34));
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TC_Switch # (.UUID(64'd51925339328697175 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_16 (.en(wire_1), .in(wire_27), .out(wire_8_1));
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TC_Switch # (.UUID(64'd1175792227051955560 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_17 (.en(wire_4), .in(wire_6), .out(wire_37));
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TC_Switch # (.UUID(64'd1768630870230821680 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_18 (.en(wire_4), .in(wire_2), .out(wire_73));
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TC_Switch # (.UUID(64'd724522933239860619 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_19 (.en(wire_4), .in(wire_14), .out(wire_8_2));
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TC_Switch # (.UUID(64'd480414198129629098 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_20 (.en(wire_16), .in(wire_2), .out(wire_41));
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TC_Switch # (.UUID(64'd2236984552964180078 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_21 (.en(wire_16), .in(wire_6), .out(wire_71));
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TC_Switch # (.UUID(64'd2331894452996132707 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_22 (.en(wire_16), .in(wire_36), .out(wire_8_3));
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TC_And # (.UUID(64'd4486090735793310582 ^ UUID), .BIT_WIDTH(64'd8)) And8_23 (.in0(wire_71), .in1(wire_41), .out(wire_36));
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TC_Nor # (.UUID(64'd428177551435513699 ^ UUID), .BIT_WIDTH(64'd8)) Nor8_24 (.in0(wire_37), .in1(wire_73), .out(wire_14));
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TC_Or # (.UUID(64'd1391410677810137682 ^ UUID), .BIT_WIDTH(64'd8)) Or8_25 (.in0(wire_39), .in1(wire_60), .out(wire_52));
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TC_Nand # (.UUID(64'd4025048423625330072 ^ UUID), .BIT_WIDTH(64'd8)) Nand8_26 (.in0(wire_34), .in1(wire_66), .out(wire_27));
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TC_Decoder3 # (.UUID(64'd3807680616509469728 ^ UUID)) Decoder3_27 (.dis(1'd0), .sel0(wire_69), .sel1(wire_42), .sel2(wire_31), .out0(wire_25), .out1(wire_30), .out2(wire_20), .out3(wire_75), .out4(wire_74), .out5(wire_46), .out6(wire_61), .out7(wire_70));
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TC_Xnor # (.UUID(64'd4268350311478768457 ^ UUID), .BIT_WIDTH(64'd8)) Xnor8_28 (.in0(wire_49), .in1(wire_81), .out(wire_59));
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TC_Xor # (.UUID(64'd4527214351160864442 ^ UUID), .BIT_WIDTH(64'd8)) Xor8_29 (.in0(wire_64), .in1(wire_12), .out(wire_40));
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TC_Not # (.UUID(64'd3618579806912338026 ^ UUID), .BIT_WIDTH(64'd8)) Not8_30 (.in(wire_58), .out(wire_63));
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TC_Mul # (.UUID(64'd86800450212264749 ^ UUID), .BIT_WIDTH(64'd8)) Mul8_31 (.in0(wire_51), .in1(wire_56), .out0(wire_80), .out1(wire_65));
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TC_Ashr # (.UUID(64'd4224934934216498493 ^ UUID), .BIT_WIDTH(64'd8)) Ashr8_32 (.in(wire_19), .shift(wire_53), .out(wire_43));
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TC_Neg # (.UUID(64'd687800544475925346 ^ UUID), .BIT_WIDTH(64'd8)) Neg8_33 (.in(wire_11), .out(wire_67));
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TC_Rol # (.UUID(64'd1317775489477211882 ^ UUID), .BIT_WIDTH(64'd8)) Rol8_34 (.in(wire_47), .shift(wire_9), .out(wire_3));
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TC_Ror # (.UUID(64'd703554170280240747 ^ UUID), .BIT_WIDTH(64'd8)) Ror8_35 (.in(wire_76), .shift(wire_54), .out(wire_18));
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TC_Shr # (.UUID(64'd3748108855456900138 ^ UUID), .BIT_WIDTH(64'd8)) Shr8_36 (.in(wire_17), .shift(wire_50), .out(wire_38));
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TC_Shl # (.UUID(64'd2176974598361832761 ^ UUID), .BIT_WIDTH(64'd8)) Shl8_37 (.in(wire_85), .shift(wire_57), .out(wire_83));
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TC_Switch # (.UUID(64'd4483630066362025873 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_38 (.en(wire_0), .in(wire_2), .out(wire_12));
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TC_Switch # (.UUID(64'd3908274583674926227 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_39 (.en(wire_0), .in(wire_6), .out(wire_64));
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TC_Switch # (.UUID(64'd4553681126267151464 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_40 (.en(wire_0), .in(wire_40), .out(wire_8_5));
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TC_Switch # (.UUID(64'd4186982137889621636 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_41 (.en(wire_24), .in(wire_2), .out(wire_81));
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TC_Switch # (.UUID(64'd1386256187545231870 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_42 (.en(wire_24), .in(wire_6), .out(wire_49));
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TC_Switch # (.UUID(64'd2659168137376368183 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_43 (.en(wire_24), .in(wire_59), .out(wire_8_4));
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TC_Switch # (.UUID(64'd1704066470517955937 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_44 (.en(wire_26), .in(wire_6), .out(wire_58));
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TC_Switch # (.UUID(64'd2990116238052745508 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_45 (.en(wire_26), .in(wire_63), .out(wire_8_6));
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TC_Switch # (.UUID(64'd2820576902535906486 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_46 (.en(wire_5), .in(wire_2), .out(wire_53));
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TC_Switch # (.UUID(64'd59631099816967048 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_47 (.en(wire_5), .in(wire_6), .out(wire_19));
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TC_Switch # (.UUID(64'd3451848842388615139 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_48 (.en(wire_5), .in(wire_43), .out(wire_22_3));
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TC_Switch # (.UUID(64'd4081918304701245721 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_49 (.en(wire_24), .in(wire_6), .out(wire_11));
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TC_Switch # (.UUID(64'd918819339348151073 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_50 (.en(wire_24), .in(wire_67), .out(wire_15_3));
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TC_Switch # (.UUID(64'd2919540118461118324 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_51 (.en(wire_1), .in(wire_6), .out(wire_79));
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TC_Switch # (.UUID(64'd3749247787192934141 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_52 (.en(wire_4), .in(wire_2), .out(wire_56));
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TC_Switch # (.UUID(64'd2395464300934186678 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_53 (.en(wire_4), .in(wire_6), .out(wire_51));
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TC_Switch # (.UUID(64'd1468357425860970596 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_54 (.en(wire_1), .in(wire_10), .out(wire_22_0));
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TC_Switch # (.UUID(64'd3788856213916320068 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_55 (.en(wire_1), .in(wire_78), .out(wire_44_0));
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TC_Switch # (.UUID(64'd3734865121253732914 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_56 (.en(wire_4), .in(wire_80), .out(wire_22_1));
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TC_Switch # (.UUID(64'd3847724417649658373 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_57 (.en(wire_4), .in(wire_65), .out(wire_44_1));
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TC_Switch # (.UUID(64'd2706629240204870554 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_58 (.en(wire_5), .in(wire_2), .out(wire_9));
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TC_Switch # (.UUID(64'd2001149239728006462 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_59 (.en(wire_5), .in(wire_6), .out(wire_47));
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TC_Switch # (.UUID(64'd2870113753177518410 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_60 (.en(wire_1), .in(wire_2), .out(wire_54));
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TC_Switch # (.UUID(64'd340004962580308093 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_61 (.en(wire_1), .in(wire_6), .out(wire_76));
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TC_Switch # (.UUID(64'd1684711578759063957 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_62 (.en(wire_4), .in(wire_6), .out(wire_17));
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TC_Switch # (.UUID(64'd2389968685784586327 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_63 (.en(wire_16), .in(wire_2), .out(wire_57));
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TC_Switch # (.UUID(64'd4535804765991235387 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_64 (.en(wire_16), .in(wire_6), .out(wire_85));
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TC_Switch # (.UUID(64'd667890680105453361 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_65 (.en(wire_4), .in(wire_2), .out(wire_50));
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TC_Switch # (.UUID(64'd3924371852208470488 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_66 (.en(wire_1), .in(wire_18), .out(wire_15_2));
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TC_Switch # (.UUID(64'd4550216520043673402 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_67 (.en(wire_5), .in(wire_3), .out(wire_15_4));
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TC_Switch # (.UUID(64'd1040267906917435020 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_68 (.en(wire_4), .in(wire_38), .out(wire_15_0));
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TC_Switch # (.UUID(64'd1068858050083309300 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_69 (.en(wire_16), .in(wire_83), .out(wire_15_1));
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TC_Switch # (.UUID(64'd1056292847970768806 ^ UUID), .BIT_WIDTH(64'd1)) Switch1_70 (.en(wire_24), .in(wire_23), .out(wire_13_0));
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TC_Switch # (.UUID(64'd2775044829367273609 ^ UUID), .BIT_WIDTH(64'd1)) Switch1_71 (.en(wire_16), .in(wire_21), .out(wire_13_1));
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TC_Switch # (.UUID(64'd683797453120618047 ^ UUID), .BIT_WIDTH(64'd8)) Output8z_72 (.en(wire_35), .in(wire_44), .out(D));
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TC_Switch # (.UUID(64'd1344327710761016922 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_73 (.en(wire_25), .in(wire_8), .out(wire_32_2));
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TC_Switch # (.UUID(64'd3164243025886628350 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_74 (.en(wire_30), .in(wire_22), .out(wire_32_1));
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TC_Switch # (.UUID(64'd389001382807605908 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_75 (.en(wire_20), .in(wire_15), .out(wire_32_0));
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TC_Or # (.UUID(64'd2298387723272408160 ^ UUID), .BIT_WIDTH(64'd1)) Or_76 (.in0(wire_1), .in1(wire_4), .out(wire_28));
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TC_And # (.UUID(64'd4016989336483643045 ^ UUID), .BIT_WIDTH(64'd1)) And_77 (.in0(wire_28), .in1(wire_30), .out(wire_35));
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TC_Mul # (.UUID(64'd3859724630390996553 ^ UUID), .BIT_WIDTH(64'd8)) DivMod8_78 (.in0(wire_79), .in1(wire_77), .out0(wire_10), .out1(wire_78));
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TC_Switch # (.UUID(64'd2129354784258529228 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_79 (.en(wire_1), .in(wire_2), .out());
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TC_Constant # (.UUID(64'd1325873776756270234 ^ UUID), .BIT_WIDTH(64'd8), .value(8'hAA)) Constant8_80 (.out(wire_77));
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wire [0:0] wire_0;
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wire [0:0] wire_1;
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wire [7:0] wire_2;
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assign wire_2 = B;
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wire [7:0] wire_3;
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wire [0:0] wire_4;
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wire [0:0] wire_5;
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wire [7:0] wire_6;
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assign wire_6 = A;
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wire [0:0] wire_7;
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wire [7:0] wire_8;
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wire [7:0] wire_8_0;
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wire [7:0] wire_8_1;
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wire [7:0] wire_8_2;
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wire [7:0] wire_8_3;
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wire [7:0] wire_8_4;
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wire [7:0] wire_8_5;
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wire [7:0] wire_8_6;
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assign wire_8 = wire_8_0|wire_8_1|wire_8_2|wire_8_3|wire_8_4|wire_8_5|wire_8_6;
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wire [7:0] wire_9;
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wire [7:0] wire_10;
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wire [7:0] wire_11;
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wire [7:0] wire_12;
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wire [0:0] wire_13;
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wire [0:0] wire_13_0;
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wire [0:0] wire_13_1;
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assign wire_13 = wire_13_0|wire_13_1;
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assign CF = wire_13;
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wire [7:0] wire_14;
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wire [7:0] wire_15;
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wire [7:0] wire_15_0;
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wire [7:0] wire_15_1;
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wire [7:0] wire_15_2;
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wire [7:0] wire_15_3;
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wire [7:0] wire_15_4;
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assign wire_15 = wire_15_0|wire_15_1|wire_15_2|wire_15_3|wire_15_4;
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wire [0:0] wire_16;
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wire [7:0] wire_17;
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wire [7:0] wire_18;
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wire [7:0] wire_19;
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wire [0:0] wire_20;
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wire [0:0] wire_21;
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||||||
|
wire [7:0] wire_22;
|
||||||
|
wire [7:0] wire_22_0;
|
||||||
|
wire [7:0] wire_22_1;
|
||||||
|
wire [7:0] wire_22_2;
|
||||||
|
wire [7:0] wire_22_3;
|
||||||
|
wire [7:0] wire_22_4;
|
||||||
|
assign wire_22 = wire_22_0|wire_22_1|wire_22_2|wire_22_3|wire_22_4;
|
||||||
|
wire [0:0] wire_23;
|
||||||
|
wire [0:0] wire_24;
|
||||||
|
wire [0:0] wire_25;
|
||||||
|
wire [0:0] wire_26;
|
||||||
|
wire [7:0] wire_27;
|
||||||
|
wire [0:0] wire_28;
|
||||||
|
wire [7:0] wire_29;
|
||||||
|
assign wire_29 = Instruction;
|
||||||
|
wire [0:0] wire_30;
|
||||||
|
wire [0:0] wire_31;
|
||||||
|
wire [7:0] wire_32;
|
||||||
|
wire [7:0] wire_32_0;
|
||||||
|
wire [7:0] wire_32_1;
|
||||||
|
wire [7:0] wire_32_2;
|
||||||
|
assign wire_32 = wire_32_0|wire_32_1|wire_32_2;
|
||||||
|
assign C = wire_32;
|
||||||
|
wire [7:0] wire_33;
|
||||||
|
wire [7:0] wire_34;
|
||||||
|
wire [0:0] wire_35;
|
||||||
|
assign D_OUT_EN = wire_35;
|
||||||
|
wire [7:0] wire_36;
|
||||||
|
wire [7:0] wire_37;
|
||||||
|
wire [7:0] wire_38;
|
||||||
|
wire [7:0] wire_39;
|
||||||
|
wire [7:0] wire_40;
|
||||||
|
wire [7:0] wire_41;
|
||||||
|
wire [0:0] wire_42;
|
||||||
|
wire [7:0] wire_43;
|
||||||
|
wire [7:0] wire_44;
|
||||||
|
wire [7:0] wire_44_0;
|
||||||
|
wire [7:0] wire_44_1;
|
||||||
|
assign wire_44 = wire_44_0|wire_44_1;
|
||||||
|
wire [7:0] wire_45;
|
||||||
|
wire [0:0] wire_46;
|
||||||
|
wire [7:0] wire_47;
|
||||||
|
wire [0:0] wire_48;
|
||||||
|
wire [7:0] wire_49;
|
||||||
|
wire [7:0] wire_50;
|
||||||
|
wire [7:0] wire_51;
|
||||||
|
wire [7:0] wire_52;
|
||||||
|
wire [7:0] wire_53;
|
||||||
|
wire [7:0] wire_54;
|
||||||
|
wire [0:0] wire_55;
|
||||||
|
wire [7:0] wire_56;
|
||||||
|
wire [7:0] wire_57;
|
||||||
|
wire [7:0] wire_58;
|
||||||
|
wire [7:0] wire_59;
|
||||||
|
wire [7:0] wire_60;
|
||||||
|
wire [0:0] wire_61;
|
||||||
|
wire [7:0] wire_62;
|
||||||
|
wire [7:0] wire_63;
|
||||||
|
wire [7:0] wire_64;
|
||||||
|
wire [7:0] wire_65;
|
||||||
|
wire [7:0] wire_66;
|
||||||
|
wire [7:0] wire_67;
|
||||||
|
wire [7:0] wire_68;
|
||||||
|
wire [0:0] wire_69;
|
||||||
|
wire [0:0] wire_70;
|
||||||
|
wire [7:0] wire_71;
|
||||||
|
wire [7:0] wire_72;
|
||||||
|
wire [7:0] wire_73;
|
||||||
|
wire [0:0] wire_74;
|
||||||
|
wire [0:0] wire_75;
|
||||||
|
wire [7:0] wire_76;
|
||||||
|
wire [7:0] wire_77;
|
||||||
|
wire [7:0] wire_78;
|
||||||
|
wire [7:0] wire_79;
|
||||||
|
wire [7:0] wire_80;
|
||||||
|
wire [7:0] wire_81;
|
||||||
|
wire [0:0] wire_82;
|
||||||
|
wire [7:0] wire_83;
|
||||||
|
wire [7:0] wire_84;
|
||||||
|
wire [7:0] wire_85;
|
||||||
|
wire [7:0] wire_86;
|
||||||
|
|
||||||
|
endmodule
|
||||||
27
src/verilog/ECP8_components/RegisterPlus.v
Normal file
27
src/verilog/ECP8_components/RegisterPlus.v
Normal file
@@ -0,0 +1,27 @@
|
|||||||
|
module RegisterPlus (clk, rst, Load, Save_value, Save, Always_output, Output);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
input wire clk;
|
||||||
|
input wire rst;
|
||||||
|
|
||||||
|
input wire [0:0] Load;
|
||||||
|
input wire [7:0] Save_value;
|
||||||
|
input wire [0:0] Save;
|
||||||
|
output wire [7:0] Always_output;
|
||||||
|
output wire [7:0] Output;
|
||||||
|
|
||||||
|
TC_Register # (.UUID(64'd1 ^ UUID), .BIT_WIDTH(64'd8)) Register8_0 (.clk(clk), .rst(rst), .load(wire_2), .save(wire_4), .in(wire_0), .out(wire_3));
|
||||||
|
TC_Constant # (.UUID(64'd2 ^ UUID), .BIT_WIDTH(64'd1), .value(1'd1)) On_1 (.out(wire_2));
|
||||||
|
TC_Switch # (.UUID(64'd3587491547824661070 ^ UUID), .BIT_WIDTH(64'd8)) Output8z_2 (.en(wire_1), .in(wire_3), .out(Output));
|
||||||
|
|
||||||
|
wire [7:0] wire_0;
|
||||||
|
assign wire_0 = Save_value;
|
||||||
|
wire [0:0] wire_1;
|
||||||
|
assign wire_1 = Load;
|
||||||
|
wire [0:0] wire_2;
|
||||||
|
wire [7:0] wire_3;
|
||||||
|
assign Always_output = wire_3;
|
||||||
|
wire [0:0] wire_4;
|
||||||
|
assign wire_4 = Save;
|
||||||
|
|
||||||
|
endmodule
|
||||||
53
src/verilog/ECP8_components/subsys/COND.v
Normal file
53
src/verilog/ECP8_components/subsys/COND.v
Normal file
@@ -0,0 +1,53 @@
|
|||||||
|
module COND (clk, rst, Condition, Input, Result);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
input wire clk;
|
||||||
|
input wire rst;
|
||||||
|
|
||||||
|
input wire [7:0] Condition;
|
||||||
|
input wire [7:0] Input;
|
||||||
|
output wire [0:0] Result;
|
||||||
|
|
||||||
|
TC_Splitter8 # (.UUID(64'd1888394345583920379 ^ UUID)) Splitter8_0 (.in(wire_14), .out0(wire_5), .out1(wire_8), .out2(wire_1), .out3(), .out4(), .out5(), .out6(), .out7());
|
||||||
|
TC_Splitter8 # (.UUID(64'd2530385753961839292 ^ UUID)) Splitter8_1 (.in(wire_17), .out0(wire_4), .out1(wire_13), .out2(wire_18), .out3(wire_3), .out4(wire_15), .out5(wire_9), .out6(wire_11), .out7(wire_0));
|
||||||
|
TC_Nor # (.UUID(64'd1517918423970542383 ^ UUID), .BIT_WIDTH(64'd1)) Nor_2 (.in0(wire_4), .in1(wire_13), .out(wire_19));
|
||||||
|
TC_Nor # (.UUID(64'd2736061366789794415 ^ UUID), .BIT_WIDTH(64'd1)) Nor_3 (.in0(wire_18), .in1(wire_3), .out(wire_23));
|
||||||
|
TC_Nor # (.UUID(64'd3648822797009876962 ^ UUID), .BIT_WIDTH(64'd1)) Nor_4 (.in0(wire_15), .in1(wire_9), .out(wire_20));
|
||||||
|
TC_Nor # (.UUID(64'd3623192028484125320 ^ UUID), .BIT_WIDTH(64'd1)) Nor_5 (.in0(wire_11), .in1(wire_0), .out(wire_21));
|
||||||
|
TC_Nand # (.UUID(64'd1210610590039792679 ^ UUID), .BIT_WIDTH(64'd1)) Nand_6 (.in0(wire_19), .in1(wire_23), .out(wire_6));
|
||||||
|
TC_Nand # (.UUID(64'd722301827588141756 ^ UUID), .BIT_WIDTH(64'd1)) Nand_7 (.in0(wire_20), .in1(wire_21), .out(wire_10));
|
||||||
|
TC_Nor # (.UUID(64'd3626258032196188357 ^ UUID), .BIT_WIDTH(64'd1)) Nor_8 (.in0(wire_6), .in1(wire_10), .out(wire_16));
|
||||||
|
TC_Switch # (.UUID(64'd2273941197800776416 ^ UUID), .BIT_WIDTH(64'd1)) Switch1_9 (.en(wire_5), .in(wire_16), .out(wire_2));
|
||||||
|
TC_Switch # (.UUID(64'd1588245332332211989 ^ UUID), .BIT_WIDTH(64'd1)) Switch1_10 (.en(wire_8), .in(wire_0), .out(wire_22));
|
||||||
|
TC_Or # (.UUID(64'd407901765067939990 ^ UUID), .BIT_WIDTH(64'd1)) Or_11 (.in0(wire_2), .in1(wire_22), .out(wire_7));
|
||||||
|
TC_Xor # (.UUID(64'd4237747319249404280 ^ UUID), .BIT_WIDTH(64'd1)) Xor_12 (.in0(wire_1), .in1(wire_7), .out(wire_12));
|
||||||
|
|
||||||
|
wire [0:0] wire_0;
|
||||||
|
wire [0:0] wire_1;
|
||||||
|
wire [0:0] wire_2;
|
||||||
|
wire [0:0] wire_3;
|
||||||
|
wire [0:0] wire_4;
|
||||||
|
wire [0:0] wire_5;
|
||||||
|
wire [0:0] wire_6;
|
||||||
|
wire [0:0] wire_7;
|
||||||
|
wire [0:0] wire_8;
|
||||||
|
wire [0:0] wire_9;
|
||||||
|
wire [0:0] wire_10;
|
||||||
|
wire [0:0] wire_11;
|
||||||
|
wire [0:0] wire_12;
|
||||||
|
assign Result = wire_12;
|
||||||
|
wire [0:0] wire_13;
|
||||||
|
wire [7:0] wire_14;
|
||||||
|
assign wire_14 = Condition;
|
||||||
|
wire [0:0] wire_15;
|
||||||
|
wire [0:0] wire_16;
|
||||||
|
wire [7:0] wire_17;
|
||||||
|
assign wire_17 = Input;
|
||||||
|
wire [0:0] wire_18;
|
||||||
|
wire [0:0] wire_19;
|
||||||
|
wire [0:0] wire_20;
|
||||||
|
wire [0:0] wire_21;
|
||||||
|
wire [0:0] wire_22;
|
||||||
|
wire [0:0] wire_23;
|
||||||
|
|
||||||
|
endmodule
|
||||||
29
src/verilog/ECP8_components/subsys/DEC.v
Normal file
29
src/verilog/ECP8_components/subsys/DEC.v
Normal file
@@ -0,0 +1,29 @@
|
|||||||
|
module DEC (clk, rst, Instruction, IMM_EN, ALU_EN, COPY_EN, BRANCH_EN);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
input wire clk;
|
||||||
|
input wire rst;
|
||||||
|
|
||||||
|
input wire [7:0] Instruction;
|
||||||
|
output wire [0:0] IMM_EN;
|
||||||
|
output wire [0:0] ALU_EN;
|
||||||
|
output wire [0:0] COPY_EN;
|
||||||
|
output wire [0:0] BRANCH_EN;
|
||||||
|
|
||||||
|
TC_Decoder2 # (.UUID(64'd954500439059266356 ^ UUID)) Decoder2_0 (.sel0(wire_6), .sel1(wire_1), .out0(wire_2), .out1(wire_3), .out2(wire_5), .out3(wire_0));
|
||||||
|
TC_Splitter8 # (.UUID(64'd2677939290028462653 ^ UUID)) Splitter8_1 (.in(wire_4), .out0(), .out1(), .out2(), .out3(), .out4(), .out5(), .out6(wire_6), .out7(wire_1));
|
||||||
|
|
||||||
|
wire [0:0] wire_0;
|
||||||
|
assign BRANCH_EN = wire_0;
|
||||||
|
wire [0:0] wire_1;
|
||||||
|
wire [0:0] wire_2;
|
||||||
|
assign IMM_EN = wire_2;
|
||||||
|
wire [0:0] wire_3;
|
||||||
|
assign ALU_EN = wire_3;
|
||||||
|
wire [7:0] wire_4;
|
||||||
|
assign wire_4 = Instruction;
|
||||||
|
wire [0:0] wire_5;
|
||||||
|
assign COPY_EN = wire_5;
|
||||||
|
wire [0:0] wire_6;
|
||||||
|
|
||||||
|
endmodule
|
||||||
166
src/verilog/ECP8e.v
Normal file
166
src/verilog/ECP8e.v
Normal file
@@ -0,0 +1,166 @@
|
|||||||
|
module ECP8e (clk, rst, arch_output_enable, arch_output_value, arch_input_enable, arch_input_value);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
input wire clk;
|
||||||
|
input wire rst;
|
||||||
|
|
||||||
|
output wire [0:0] arch_output_enable;
|
||||||
|
output wire [7:0] arch_output_value;
|
||||||
|
output wire [0:0] arch_input_enable;
|
||||||
|
input wire [7:0] arch_input_value;
|
||||||
|
|
||||||
|
TC_Switch # (.UUID(64'd1715727152826423794 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_0 (.en(wire_50), .in(wire_48), .out(wire_41));
|
||||||
|
TC_Halt # (.UUID(64'd2976448359382631736 ^ UUID)) Halt_1 (.clk(clk), .rst(rst), .en(wire_67));
|
||||||
|
TC_Not # (.UUID(64'd2472047754744094114 ^ UUID), .BIT_WIDTH(64'd1)) Not_2 (.in(wire_61), .out(wire_67));
|
||||||
|
TC_IOSwitch # (.UUID(64'd2352853726822514667 ^ UUID), .BIT_WIDTH(64'd8)) LevelOutputArch_3 (.in(wire_56), .en(wire_38), .out(arch_output_value));
|
||||||
|
TC_Program8_1 # (.UUID(64'd2319742357034652024 ^ UUID), .DEFAULT_FILE_NAME("outport_test.bin"), .ARG_SIG("outport_test=%s")) Program8_1_4 (.clk(clk), .rst(rst), .address(wire_5), .out(wire_48));
|
||||||
|
TC_Switch # (.UUID(64'd556654018140205888 ^ UUID), .BIT_WIDTH(64'd8)) LevelInputArch_5 (.en(wire_27), .in(arch_input_value), .out(wire_39));
|
||||||
|
ALU # (.UUID(64'd3424272698184478142 ^ UUID)) ALU_6 (.clk(clk), .rst(rst), .Instruction(wire_41), .A(wire_35), .B(wire_75), .D_OUT_EN(wire_15), .D(wire_71), .CF(), .C(wire_66));
|
||||||
|
TC_Ram # (.UUID(64'd1661974221341126710 ^ UUID), .WORD_WIDTH(64'd8), .WORD_COUNT(64'd64)) Ram_7 (.clk(clk), .rst(rst), .load(1'd0), .save(1'd0), .address(32'd0), .in0(64'd0), .in1(64'd0), .in2(64'd0), .in3(64'd0), .out0(), .out1(), .out2(), .out3());
|
||||||
|
TC_Buffer # (.UUID(64'd3602924629092547678 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_8 (.in(wire_48), .out(wire_28));
|
||||||
|
TC_Buffer # (.UUID(64'd1036402492479265627 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_9 (.in(wire_1), .out(wire_55));
|
||||||
|
TC_Buffer # (.UUID(64'd3234323155509956945 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_10 (.in(wire_23), .out(wire_60));
|
||||||
|
TC_Buffer # (.UUID(64'd2118082778336995084 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_11 (.in(wire_18), .out(wire_77));
|
||||||
|
TC_Buffer # (.UUID(64'd3247628008814229228 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_12 (.in(wire_20), .out(wire_72));
|
||||||
|
TC_Buffer # (.UUID(64'd3783645420539942969 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_13 (.in(wire_33), .out(wire_73));
|
||||||
|
TC_Buffer # (.UUID(64'd101493406757515111 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_14 (.in(wire_31), .out(wire_43));
|
||||||
|
TC_Buffer # (.UUID(64'd1648258134768700275 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_15 (.in(wire_2), .out(wire_56));
|
||||||
|
TC_Buffer # (.UUID(64'd297196408869131089 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_16 (.in(wire_39), .out(wire_51));
|
||||||
|
TC_Decoder3 # (.UUID(64'd319890292667874856 ^ UUID)) Decoder3_17 (.dis(wire_19), .sel0(wire_47), .sel1(wire_69), .sel2(wire_70), .out0(wire_32), .out1(wire_34), .out2(wire_46), .out3(wire_9), .out4(wire_7), .out5(wire_62), .out6(wire_26), .out7(wire_53));
|
||||||
|
TC_Decoder3 # (.UUID(64'd4421418411989485663 ^ UUID)) Decoder3_18 (.dis(wire_19), .sel0(wire_52), .sel1(wire_58), .sel2(wire_4), .out0(wire_65), .out1(wire_44), .out2(wire_59), .out3(wire_54), .out4(wire_14), .out5(wire_21), .out6(wire_24), .out7(wire_42));
|
||||||
|
TC_Splitter8 # (.UUID(64'd274394922392375603 ^ UUID)) Splitter8_19 (.in(wire_28), .out0(wire_52), .out1(wire_58), .out2(wire_4), .out3(wire_47), .out4(wire_69), .out5(wire_70), .out6(), .out7());
|
||||||
|
TC_Maker16 # (.UUID(64'd4271331395148101399 ^ UUID)) Maker16_20 (.in0(wire_23), .in1(wire_18), .out(wire_64));
|
||||||
|
TC_Xor # (.UUID(64'd4015117391550831776 ^ UUID), .BIT_WIDTH(64'd1)) Xor_21 (.in0(wire_45), .in1(wire_65), .out(wire_68));
|
||||||
|
TC_Switch # (.UUID(64'd4445417212749692549 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_22 (.en(wire_26), .in(wire_51), .out(wire_6_1));
|
||||||
|
TC_Switch # (.UUID(64'd556730729123347464 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_23 (.en(wire_24), .in(wire_17), .out(wire_2));
|
||||||
|
TC_Buffer # (.UUID(64'd3347726601253752187 ^ UUID), .BIT_WIDTH(64'd1)) Buffer1_24 (.in(wire_10), .out(wire_50));
|
||||||
|
TC_Switch # (.UUID(64'd1860343635038049181 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_25 (.en(wire_8), .in(wire_17), .out(wire_6_0));
|
||||||
|
TC_Or # (.UUID(64'd4336129294321593228 ^ UUID), .BIT_WIDTH(64'd1)) Or_26 (.in0(wire_25), .in1(wire_3), .out(wire_45));
|
||||||
|
TC_Xor # (.UUID(64'd1518074666294394017 ^ UUID), .BIT_WIDTH(64'd1)) Xor_27 (.in0(wire_54), .in1(wire_10), .out(wire_12));
|
||||||
|
TC_Nand # (.UUID(64'd3859693831101792233 ^ UUID), .BIT_WIDTH(64'd1)) Nand_28 (.in0(wire_42), .in1(wire_53), .out(wire_22));
|
||||||
|
TC_Switch # (.UUID(64'd1247979186234576792 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_29 (.en(wire_3), .in(wire_28), .out(wire_6_4));
|
||||||
|
TC_Or3 # (.UUID(64'd4011049292989256787 ^ UUID), .BIT_WIDTH(64'd1)) Or3_30 (.in0(wire_3), .in1(wire_10), .in2(wire_25), .out(wire_19));
|
||||||
|
TC_Switch # (.UUID(64'd2893193334261668714 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_31 (.en(wire_10), .in(wire_16), .out(wire_6_3));
|
||||||
|
TC_And # (.UUID(64'd3005434726623612484 ^ UUID), .BIT_WIDTH(64'd1)) And_32 (.in0(wire_25), .in1(wire_76), .out(wire_49));
|
||||||
|
TC_Switch # (.UUID(64'd929078426947889085 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_33 (.en(wire_25), .in(wire_28), .out(wire_63));
|
||||||
|
TC_Counter # (.UUID(64'd3263272588803768522 ^ UUID), .BIT_WIDTH(64'd8), .count(8'd1)) Counter8_34 (.clk(clk), .rst(rst), .save(wire_49), .in(wire_1), .out(wire_5));
|
||||||
|
TC_Buffer # (.UUID(64'd2235373354836046298 ^ UUID), .BIT_WIDTH(64'd1)) Buffer1_35 (.in(wire_22), .out(wire_61));
|
||||||
|
TC_Buffer # (.UUID(64'd2032593801523540386 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_36 (.in(wire_5), .out());
|
||||||
|
TC_Buffer # (.UUID(64'd2286316240340576623 ^ UUID), .BIT_WIDTH(64'd1)) Buffer1_37 (.in(wire_15), .out(wire_36));
|
||||||
|
TC_Splitter16 # (.UUID(64'd2817158020377327923 ^ UUID)) Splitter16_38 (.in(wire_29), .out0(wire_16), .out1(wire_0));
|
||||||
|
TC_Switch # (.UUID(64'd2251356442933710957 ^ UUID), .BIT_WIDTH(64'd8)) Switch8_39 (.en(wire_36), .in(wire_0), .out(wire_6_2));
|
||||||
|
TC_Buffer # (.UUID(64'd2774123988237700806 ^ UUID), .BIT_WIDTH(64'd1)) Buffer1_40 (.in(wire_24), .out(wire_38));
|
||||||
|
TC_Buffer # (.UUID(64'd2259435457617166464 ^ UUID), .BIT_WIDTH(64'd1)) Buffer1_41 (.in(wire_26), .out(wire_27));
|
||||||
|
TC_Nor # (.UUID(64'd28166036220749041 ^ UUID), .BIT_WIDTH(64'd1)) Nor_42 (.in0(wire_26), .in1(wire_24), .out(wire_37));
|
||||||
|
TC_And # (.UUID(64'd2711603589399634934 ^ UUID), .BIT_WIDTH(64'd1)) And_43 (.in0(wire_40), .in1(wire_37), .out(wire_8));
|
||||||
|
TC_Splitter16 # (.UUID(64'd4364533521657012903 ^ UUID)) Splitter16_44 (.in(wire_74), .out0(wire_11), .out1(wire_30));
|
||||||
|
TC_Buffer # (.UUID(64'd1306800471778976915 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_45 (.in(wire_11), .out(wire_35));
|
||||||
|
TC_Buffer # (.UUID(64'd4600618263124473635 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_46 (.in(wire_30), .out(wire_75));
|
||||||
|
TC_Switch # (.UUID(64'd2102499097582599256 ^ UUID), .BIT_WIDTH(64'd16)) Switch16_47 (.en(wire_10), .in(wire_64), .out(wire_74));
|
||||||
|
TC_Buffer # (.UUID(64'd1794452372346720268 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_48 (.in(wire_66), .out(wire_57));
|
||||||
|
TC_Buffer # (.UUID(64'd3772267359649597453 ^ UUID), .BIT_WIDTH(64'd8)) Buffer8_49 (.in(wire_71), .out(wire_13));
|
||||||
|
TC_Maker16 # (.UUID(64'd1181495850574424 ^ UUID)) Maker16_50 (.in0(wire_57), .in1(wire_13), .out(wire_29));
|
||||||
|
RegisterPlus # (.UUID(64'd2661760033600874299 ^ UUID)) RegisterPlus_51 (.clk(clk), .rst(rst), .Load(wire_32), .Save_value(wire_6), .Save(wire_68), .Always_output(wire_1), .Output(wire_17_4));
|
||||||
|
RegisterPlus # (.UUID(64'd2163217265803647012 ^ UUID)) RegisterPlus_52 (.clk(clk), .rst(rst), .Load(wire_34), .Save_value(wire_6), .Save(wire_44), .Always_output(wire_23), .Output(wire_17_5));
|
||||||
|
RegisterPlus # (.UUID(64'd1347627285814452637 ^ UUID)) RegisterPlus_53 (.clk(clk), .rst(rst), .Load(wire_46), .Save_value(wire_6), .Save(wire_59), .Always_output(wire_18), .Output(wire_17_3));
|
||||||
|
RegisterPlus # (.UUID(64'd3166915688793493761 ^ UUID)) RegisterPlus_54 (.clk(clk), .rst(rst), .Load(wire_9), .Save_value(wire_6), .Save(wire_12), .Always_output(wire_20), .Output(wire_17_2));
|
||||||
|
RegisterPlus # (.UUID(64'd4519434156825869138 ^ UUID)) RegisterPlus_55 (.clk(clk), .rst(rst), .Load(wire_7), .Save_value(wire_6), .Save(wire_14), .Always_output(wire_33), .Output(wire_17_1));
|
||||||
|
RegisterPlus # (.UUID(64'd3857793667730710479 ^ UUID)) RegisterPlus_56 (.clk(clk), .rst(rst), .Load(wire_62), .Save_value(wire_6), .Save(wire_21), .Always_output(wire_31), .Output(wire_17_0));
|
||||||
|
DEC # (.UUID(64'd3963022757837899629 ^ UUID)) DEC_57 (.clk(clk), .rst(rst), .Instruction(wire_28), .IMM_EN(wire_3), .ALU_EN(wire_10), .COPY_EN(wire_40), .BRANCH_EN(wire_25));
|
||||||
|
COND # (.UUID(64'd1986738645304097046 ^ UUID)) COND_58 (.clk(clk), .rst(rst), .Condition(wire_63), .Input(wire_20), .Result(wire_76));
|
||||||
|
|
||||||
|
wire [7:0] wire_0;
|
||||||
|
wire [7:0] wire_1;
|
||||||
|
wire [7:0] wire_2;
|
||||||
|
wire [0:0] wire_3;
|
||||||
|
wire [0:0] wire_4;
|
||||||
|
wire [7:0] wire_5;
|
||||||
|
wire [7:0] wire_6;
|
||||||
|
wire [7:0] wire_6_0;
|
||||||
|
wire [7:0] wire_6_1;
|
||||||
|
wire [7:0] wire_6_2;
|
||||||
|
wire [7:0] wire_6_3;
|
||||||
|
wire [7:0] wire_6_4;
|
||||||
|
assign wire_6 = wire_6_0|wire_6_1|wire_6_2|wire_6_3|wire_6_4;
|
||||||
|
wire [0:0] wire_7;
|
||||||
|
wire [0:0] wire_8;
|
||||||
|
wire [0:0] wire_9;
|
||||||
|
wire [0:0] wire_10;
|
||||||
|
wire [7:0] wire_11;
|
||||||
|
wire [0:0] wire_12;
|
||||||
|
wire [7:0] wire_13;
|
||||||
|
wire [0:0] wire_14;
|
||||||
|
wire [0:0] wire_15;
|
||||||
|
wire [7:0] wire_16;
|
||||||
|
wire [7:0] wire_17;
|
||||||
|
wire [7:0] wire_17_0;
|
||||||
|
wire [7:0] wire_17_1;
|
||||||
|
wire [7:0] wire_17_2;
|
||||||
|
wire [7:0] wire_17_3;
|
||||||
|
wire [7:0] wire_17_4;
|
||||||
|
wire [7:0] wire_17_5;
|
||||||
|
assign wire_17 = wire_17_0|wire_17_1|wire_17_2|wire_17_3|wire_17_4|wire_17_5;
|
||||||
|
wire [7:0] wire_18;
|
||||||
|
wire [0:0] wire_19;
|
||||||
|
wire [7:0] wire_20;
|
||||||
|
wire [0:0] wire_21;
|
||||||
|
wire [0:0] wire_22;
|
||||||
|
wire [7:0] wire_23;
|
||||||
|
wire [0:0] wire_24;
|
||||||
|
wire [0:0] wire_25;
|
||||||
|
wire [0:0] wire_26;
|
||||||
|
wire [0:0] wire_27;
|
||||||
|
assign arch_input_enable = wire_27;
|
||||||
|
wire [7:0] wire_28;
|
||||||
|
wire [15:0] wire_29;
|
||||||
|
wire [7:0] wire_30;
|
||||||
|
wire [7:0] wire_31;
|
||||||
|
wire [0:0] wire_32;
|
||||||
|
wire [7:0] wire_33;
|
||||||
|
wire [0:0] wire_34;
|
||||||
|
wire [7:0] wire_35;
|
||||||
|
wire [0:0] wire_36;
|
||||||
|
wire [0:0] wire_37;
|
||||||
|
wire [0:0] wire_38;
|
||||||
|
assign arch_output_enable = wire_38;
|
||||||
|
wire [7:0] wire_39;
|
||||||
|
wire [0:0] wire_40;
|
||||||
|
wire [7:0] wire_41;
|
||||||
|
wire [0:0] wire_42;
|
||||||
|
wire [7:0] wire_43;
|
||||||
|
wire [0:0] wire_44;
|
||||||
|
wire [0:0] wire_45;
|
||||||
|
wire [0:0] wire_46;
|
||||||
|
wire [0:0] wire_47;
|
||||||
|
wire [7:0] wire_48;
|
||||||
|
wire [0:0] wire_49;
|
||||||
|
wire [0:0] wire_50;
|
||||||
|
wire [7:0] wire_51;
|
||||||
|
wire [0:0] wire_52;
|
||||||
|
wire [0:0] wire_53;
|
||||||
|
wire [0:0] wire_54;
|
||||||
|
wire [7:0] wire_55;
|
||||||
|
wire [7:0] wire_56;
|
||||||
|
wire [7:0] wire_57;
|
||||||
|
wire [0:0] wire_58;
|
||||||
|
wire [0:0] wire_59;
|
||||||
|
wire [7:0] wire_60;
|
||||||
|
wire [0:0] wire_61;
|
||||||
|
wire [0:0] wire_62;
|
||||||
|
wire [7:0] wire_63;
|
||||||
|
wire [15:0] wire_64;
|
||||||
|
wire [0:0] wire_65;
|
||||||
|
wire [7:0] wire_66;
|
||||||
|
wire [0:0] wire_67;
|
||||||
|
wire [0:0] wire_68;
|
||||||
|
wire [0:0] wire_69;
|
||||||
|
wire [0:0] wire_70;
|
||||||
|
wire [7:0] wire_71;
|
||||||
|
wire [7:0] wire_72;
|
||||||
|
wire [7:0] wire_73;
|
||||||
|
wire [15:0] wire_74;
|
||||||
|
wire [7:0] wire_75;
|
||||||
|
wire [0:0] wire_76;
|
||||||
|
wire [7:0] wire_77;
|
||||||
|
|
||||||
|
endmodule
|
||||||
6296
src/verilog/TC_Universe-iv.out
Executable file
6296
src/verilog/TC_Universe-iv.out
Executable file
File diff suppressed because it is too large
Load Diff
71
src/verilog/TC_Universe.v
Normal file
71
src/verilog/TC_Universe.v
Normal file
@@ -0,0 +1,71 @@
|
|||||||
|
`timescale 10ns / 1ns
|
||||||
|
|
||||||
|
module TC_Universe ();
|
||||||
|
// clock and reset signals
|
||||||
|
reg clk;
|
||||||
|
reg rst;
|
||||||
|
|
||||||
|
// test data
|
||||||
|
reg [15:0] index;
|
||||||
|
reg [7:0] mem [0:65535];
|
||||||
|
reg [1024*4:0] file_name;
|
||||||
|
|
||||||
|
integer i;
|
||||||
|
integer fd;
|
||||||
|
|
||||||
|
// dut (Design Under Test) io
|
||||||
|
reg load;
|
||||||
|
reg save;
|
||||||
|
wire control_in;
|
||||||
|
reg [7:0] data_in;
|
||||||
|
wire control_out;
|
||||||
|
wire [7:0] data_out;
|
||||||
|
|
||||||
|
// dut instantiation
|
||||||
|
ECP8e dut (.clk(clk), .rst(rst),
|
||||||
|
.arch_output_enable(control_out), .arch_output_value(data_out),
|
||||||
|
.arch_input_enable(control_in), .arch_input_value(data_in));
|
||||||
|
|
||||||
|
// generate clock
|
||||||
|
initial begin
|
||||||
|
clk = 1'b0;
|
||||||
|
forever #1 clk = ~clk;
|
||||||
|
end
|
||||||
|
|
||||||
|
// generate reset
|
||||||
|
initial begin
|
||||||
|
rst = 1'b1;
|
||||||
|
#5
|
||||||
|
rst = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
assign data_in = 0;
|
||||||
|
|
||||||
|
i = ($value$plusargs("INPUT_FILE=%s", file_name));
|
||||||
|
if (i != 0) begin
|
||||||
|
i = 0;
|
||||||
|
fd = $fopen(file_name, "r");
|
||||||
|
while (i < 65535 && !$feof(fd)) begin
|
||||||
|
mem[i] = $fgetc(fd);
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @ (posedge control_in) begin
|
||||||
|
if (!rst) begin
|
||||||
|
data_in <= mem[index];
|
||||||
|
index <= index + 1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @ (negedge clk) begin
|
||||||
|
if (control_out && !rst) begin
|
||||||
|
//i = $fputc(data_out, 32'h8000_0001);
|
||||||
|
$display("received char 0x%h", data_out);
|
||||||
|
end
|
||||||
|
if (!control_in) begin
|
||||||
|
data_in <= 0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
3
src/verilog/build-ECP8e-iverilog.sh
Executable file
3
src/verilog/build-ECP8e-iverilog.sh
Executable file
@@ -0,0 +1,3 @@
|
|||||||
|
#!/usr/bin/env bash
|
||||||
|
set -e
|
||||||
|
iverilog TC_Universe.v -o TC_Universe-iv.out -y builtin_components -y . -y "ECP8_components" -y "ECP8_components/subsys" "$@"
|
||||||
12
src/verilog/builtin_components/TC_Add.v
Normal file
12
src/verilog/builtin_components/TC_Add.v
Normal file
@@ -0,0 +1,12 @@
|
|||||||
|
module TC_Add (in0, in1, ci, out, co);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
parameter BIT_WIDTH = 1;
|
||||||
|
input [BIT_WIDTH-1:0] in0;
|
||||||
|
input [BIT_WIDTH-1:0] in1;
|
||||||
|
input ci;
|
||||||
|
output [BIT_WIDTH-1:0] out;
|
||||||
|
output co;
|
||||||
|
|
||||||
|
assign {co, out} = in0 + in1 + ci;
|
||||||
|
endmodule
|
||||||
10
src/verilog/builtin_components/TC_And.v
Normal file
10
src/verilog/builtin_components/TC_And.v
Normal file
@@ -0,0 +1,10 @@
|
|||||||
|
module TC_And(in0, in1, out);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
parameter BIT_WIDTH = 1;
|
||||||
|
input [BIT_WIDTH-1:0] in0;
|
||||||
|
input [BIT_WIDTH-1:0] in1;
|
||||||
|
output [BIT_WIDTH-1:0] out;
|
||||||
|
|
||||||
|
assign out = in0 & in1;
|
||||||
|
endmodule
|
||||||
10
src/verilog/builtin_components/TC_Ashr.v
Normal file
10
src/verilog/builtin_components/TC_Ashr.v
Normal file
@@ -0,0 +1,10 @@
|
|||||||
|
module TC_Ashr (in, shift, out);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
parameter BIT_WIDTH = 1;
|
||||||
|
input [BIT_WIDTH-1:0] in;
|
||||||
|
input [7:0] shift;
|
||||||
|
output [BIT_WIDTH-1:0] out;
|
||||||
|
|
||||||
|
assign out = in >>> shift;
|
||||||
|
endmodule
|
||||||
9
src/verilog/builtin_components/TC_Buffer.v
Normal file
9
src/verilog/builtin_components/TC_Buffer.v
Normal file
@@ -0,0 +1,9 @@
|
|||||||
|
module TC_Buffer(in, out);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
parameter BIT_WIDTH = 1;
|
||||||
|
input [BIT_WIDTH-1:0] in;
|
||||||
|
output [BIT_WIDTH-1:0] out;
|
||||||
|
|
||||||
|
assign out = in;
|
||||||
|
endmodule
|
||||||
10
src/verilog/builtin_components/TC_Constant.v
Normal file
10
src/verilog/builtin_components/TC_Constant.v
Normal file
@@ -0,0 +1,10 @@
|
|||||||
|
|
||||||
|
module TC_Constant(out);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
parameter BIT_WIDTH = 1;
|
||||||
|
parameter value = {BIT_WIDTH{1'b0}};
|
||||||
|
output [BIT_WIDTH-1:0] out;
|
||||||
|
|
||||||
|
assign out = value;
|
||||||
|
endmodule
|
||||||
33
src/verilog/builtin_components/TC_Counter.v
Normal file
33
src/verilog/builtin_components/TC_Counter.v
Normal file
@@ -0,0 +1,33 @@
|
|||||||
|
module TC_Counter (clk, rst, save, in, out);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
parameter BIT_WIDTH = 8;
|
||||||
|
parameter count = 1;
|
||||||
|
input clk;
|
||||||
|
input rst;
|
||||||
|
input save;
|
||||||
|
input [BIT_WIDTH-1:0] in;
|
||||||
|
output reg [BIT_WIDTH-1:0] out;
|
||||||
|
|
||||||
|
reg [BIT_WIDTH-1:0] value;
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
out = {BIT_WIDTH{1'b0}};
|
||||||
|
value = {BIT_WIDTH{1'b0}};
|
||||||
|
end
|
||||||
|
|
||||||
|
always @ (posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
out <= {BIT_WIDTH{1'b0}};
|
||||||
|
value <= {BIT_WIDTH{1'b0}};
|
||||||
|
end else begin
|
||||||
|
if (save) begin
|
||||||
|
out <= in;
|
||||||
|
value <= in + count;
|
||||||
|
end else begin
|
||||||
|
out <= value;
|
||||||
|
value <= value + count;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
19
src/verilog/builtin_components/TC_Decoder2.v
Normal file
19
src/verilog/builtin_components/TC_Decoder2.v
Normal file
@@ -0,0 +1,19 @@
|
|||||||
|
module TC_Decoder2 (sel0, sel1, out0, out1, out2, out3);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
input sel0;
|
||||||
|
input sel1;
|
||||||
|
output reg out0;
|
||||||
|
output reg out1;
|
||||||
|
output reg out2;
|
||||||
|
output reg out3;
|
||||||
|
|
||||||
|
always @ (sel1, sel0) begin
|
||||||
|
case({sel1, sel0})
|
||||||
|
2'b00 : {out3, out2, out1, out0} = 4'b0001;
|
||||||
|
2'b01 : {out3, out2, out1, out0} = 4'b0010;
|
||||||
|
2'b10 : {out3, out2, out1, out0} = 4'b0100;
|
||||||
|
2'b11 : {out3, out2, out1, out0} = 4'b1000;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
31
src/verilog/builtin_components/TC_Decoder3.v
Normal file
31
src/verilog/builtin_components/TC_Decoder3.v
Normal file
@@ -0,0 +1,31 @@
|
|||||||
|
module TC_Decoder3 (dis, sel0, sel1, sel2, out0, out1, out2, out3, out4, out5, out6, out7);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
input dis;
|
||||||
|
input sel0;
|
||||||
|
input sel1;
|
||||||
|
input sel2;
|
||||||
|
output reg out0;
|
||||||
|
output reg out1;
|
||||||
|
output reg out2;
|
||||||
|
output reg out3;
|
||||||
|
output reg out4;
|
||||||
|
output reg out5;
|
||||||
|
output reg out6;
|
||||||
|
output reg out7;
|
||||||
|
|
||||||
|
always @ (dis or sel2 or sel1 or sel0)
|
||||||
|
begin
|
||||||
|
case({dis, sel2, sel1, sel0})
|
||||||
|
4'b0000 : {out7, out6, out5, out4, out3, out2, out1, out0} = 8'b0000_0001;
|
||||||
|
4'b0001 : {out7, out6, out5, out4, out3, out2, out1, out0} = 8'b0000_0010;
|
||||||
|
4'b0010 : {out7, out6, out5, out4, out3, out2, out1, out0} = 8'b0000_0100;
|
||||||
|
4'b0011 : {out7, out6, out5, out4, out3, out2, out1, out0} = 8'b0000_1000;
|
||||||
|
4'b0100 : {out7, out6, out5, out4, out3, out2, out1, out0} = 8'b0001_0000;
|
||||||
|
4'b0101 : {out7, out6, out5, out4, out3, out2, out1, out0} = 8'b0010_0000;
|
||||||
|
4'b0110 : {out7, out6, out5, out4, out3, out2, out1, out0} = 8'b0100_0000;
|
||||||
|
4'b0111 : {out7, out6, out5, out4, out3, out2, out1, out0} = 8'b1000_0000;
|
||||||
|
default : {out7, out6, out5, out4, out3, out2, out1, out0} = 8'b0000_0000;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
15
src/verilog/builtin_components/TC_Halt.v
Normal file
15
src/verilog/builtin_components/TC_Halt.v
Normal file
@@ -0,0 +1,15 @@
|
|||||||
|
module TC_Halt (clk, rst, en);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
parameter HALT_MESSAGE = "";
|
||||||
|
input clk;
|
||||||
|
input rst;
|
||||||
|
input en;
|
||||||
|
|
||||||
|
always @ (negedge clk) begin
|
||||||
|
if (en) begin
|
||||||
|
$display("%s", HALT_MESSAGE);
|
||||||
|
$stop;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
17
src/verilog/builtin_components/TC_IOSwitch.v
Normal file
17
src/verilog/builtin_components/TC_IOSwitch.v
Normal file
@@ -0,0 +1,17 @@
|
|||||||
|
module TC_IOSwitch (in, en, out);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
parameter BIT_WIDTH = 1;
|
||||||
|
input en;
|
||||||
|
input [BIT_WIDTH-1:0] in;
|
||||||
|
output [BIT_WIDTH-1:0] out;
|
||||||
|
reg [BIT_WIDTH-1:0] outval;
|
||||||
|
|
||||||
|
always @ (en or in) begin
|
||||||
|
case(en)
|
||||||
|
1'b0 : outval = {BIT_WIDTH{1'b0}};
|
||||||
|
1'b1 : outval = in;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
assign out = outval;
|
||||||
|
endmodule
|
||||||
9
src/verilog/builtin_components/TC_Maker16.v
Normal file
9
src/verilog/builtin_components/TC_Maker16.v
Normal file
@@ -0,0 +1,9 @@
|
|||||||
|
module TC_Maker16 (in0, in1, out);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
input [7:0] in0;
|
||||||
|
input [7:0] in1;
|
||||||
|
output [15:0] out;
|
||||||
|
|
||||||
|
assign out = {in1, in0};
|
||||||
|
endmodule
|
||||||
12
src/verilog/builtin_components/TC_Mul.v
Normal file
12
src/verilog/builtin_components/TC_Mul.v
Normal file
@@ -0,0 +1,12 @@
|
|||||||
|
module TC_Mul (in0, in1, out0, out1);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
parameter BIT_WIDTH = 1;
|
||||||
|
input [BIT_WIDTH-1:0] in0;
|
||||||
|
input [BIT_WIDTH-1:0] in1;
|
||||||
|
output [BIT_WIDTH-1:0] out0;
|
||||||
|
output [BIT_WIDTH-1:0] out1;
|
||||||
|
|
||||||
|
assign out0 = in0 / in1;
|
||||||
|
assign out1 = in0 % in1;
|
||||||
|
endmodule
|
||||||
10
src/verilog/builtin_components/TC_Nand.v
Normal file
10
src/verilog/builtin_components/TC_Nand.v
Normal file
@@ -0,0 +1,10 @@
|
|||||||
|
module TC_Nand(in0, in1, out);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
parameter BIT_WIDTH = 1;
|
||||||
|
input [BIT_WIDTH-1:0] in0;
|
||||||
|
input [BIT_WIDTH-1:0] in1;
|
||||||
|
output [BIT_WIDTH-1:0] out;
|
||||||
|
|
||||||
|
assign out = ~(in0 & in1);
|
||||||
|
endmodule
|
||||||
9
src/verilog/builtin_components/TC_Neg.v
Normal file
9
src/verilog/builtin_components/TC_Neg.v
Normal file
@@ -0,0 +1,9 @@
|
|||||||
|
module TC_Neg (in, out);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
parameter BIT_WIDTH = 1;
|
||||||
|
input [BIT_WIDTH-1:0] in;
|
||||||
|
output [BIT_WIDTH-1:0] out;
|
||||||
|
|
||||||
|
assign out = {BIT_WIDTH{1'b0}} - in;
|
||||||
|
endmodule
|
||||||
10
src/verilog/builtin_components/TC_Nor.v
Normal file
10
src/verilog/builtin_components/TC_Nor.v
Normal file
@@ -0,0 +1,10 @@
|
|||||||
|
module TC_Nor(in0, in1, out);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
parameter BIT_WIDTH = 1;
|
||||||
|
input [BIT_WIDTH-1:0] in0;
|
||||||
|
input [BIT_WIDTH-1:0] in1;
|
||||||
|
output [BIT_WIDTH-1:0] out;
|
||||||
|
|
||||||
|
assign out = ~(in0 | in1);
|
||||||
|
endmodule
|
||||||
9
src/verilog/builtin_components/TC_Not.v
Normal file
9
src/verilog/builtin_components/TC_Not.v
Normal file
@@ -0,0 +1,9 @@
|
|||||||
|
module TC_Not(in, out);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
parameter BIT_WIDTH = 1;
|
||||||
|
input [BIT_WIDTH-1:0] in;
|
||||||
|
output [BIT_WIDTH-1:0] out;
|
||||||
|
|
||||||
|
assign out = ~in;
|
||||||
|
endmodule
|
||||||
10
src/verilog/builtin_components/TC_Or.v
Normal file
10
src/verilog/builtin_components/TC_Or.v
Normal file
@@ -0,0 +1,10 @@
|
|||||||
|
module TC_Or(in0, in1, out);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
parameter BIT_WIDTH = 1;
|
||||||
|
input [BIT_WIDTH-1:0] in0;
|
||||||
|
input [BIT_WIDTH-1:0] in1;
|
||||||
|
output [BIT_WIDTH-1:0] out;
|
||||||
|
|
||||||
|
assign out = in0 | in1;
|
||||||
|
endmodule
|
||||||
11
src/verilog/builtin_components/TC_Or3.v
Normal file
11
src/verilog/builtin_components/TC_Or3.v
Normal file
@@ -0,0 +1,11 @@
|
|||||||
|
module TC_Or3(in0, in1, in2, out);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
parameter BIT_WIDTH = 1;
|
||||||
|
input [BIT_WIDTH-1:0] in0;
|
||||||
|
input [BIT_WIDTH-1:0] in1;
|
||||||
|
input [BIT_WIDTH-1:0] in2;
|
||||||
|
output [BIT_WIDTH-1:0] out;
|
||||||
|
|
||||||
|
assign out = in0 | in1 | in2;
|
||||||
|
endmodule
|
||||||
46
src/verilog/builtin_components/TC_Program8_1.v
Normal file
46
src/verilog/builtin_components/TC_Program8_1.v
Normal file
@@ -0,0 +1,46 @@
|
|||||||
|
module TC_Program8_1 (clk, rst, address, out);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
parameter MAX_WORD_COUNT = 256;
|
||||||
|
parameter DEFAULT_FILE_NAME = "test_jumps.mem";
|
||||||
|
parameter ARG_SIG = "FILE_NAME=%s";
|
||||||
|
reg [1024*8:0] hexfile;
|
||||||
|
input clk;
|
||||||
|
input rst;
|
||||||
|
input [7:0] address;
|
||||||
|
output reg [7:0] out;
|
||||||
|
|
||||||
|
//reg [7:0] mem [0:BIT_DMAX_WORD_COUNTEPTH];
|
||||||
|
reg [7:0] mem [0:MAX_WORD_COUNT - 1];
|
||||||
|
|
||||||
|
integer fd;
|
||||||
|
integer i;
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
hexfile = DEFAULT_FILE_NAME;
|
||||||
|
$display("param %0s", hexfile);
|
||||||
|
i = ($value$plusargs(ARG_SIG, hexfile));
|
||||||
|
$display("loading %0s", hexfile);
|
||||||
|
fd = $fopen(hexfile, "r");
|
||||||
|
if (fd) begin
|
||||||
|
i = 0;
|
||||||
|
while (!$feof(fd) && i < MAX_WORD_COUNT) begin
|
||||||
|
mem[i] = $fgetc(fd);
|
||||||
|
i = i + 1;
|
||||||
|
end
|
||||||
|
$display("read %0d bytes", i);
|
||||||
|
end else begin
|
||||||
|
$display("file not found");
|
||||||
|
end
|
||||||
|
$fclose(fd);
|
||||||
|
out = 8'b0000_0000;
|
||||||
|
end
|
||||||
|
|
||||||
|
always @ (address or rst) begin
|
||||||
|
if (rst) begin
|
||||||
|
out = 8'b0000_0000;
|
||||||
|
end else begin
|
||||||
|
out = mem[address];
|
||||||
|
end
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
110
src/verilog/builtin_components/TC_Ram.v
Normal file
110
src/verilog/builtin_components/TC_Ram.v
Normal file
@@ -0,0 +1,110 @@
|
|||||||
|
module TC_Ram (clk, rst, load, save, address, in0, in1, in2, in3, out0, out1, out2, out3);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
parameter WORD_WIDTH = 256;
|
||||||
|
parameter WORD_COUNT = 256;
|
||||||
|
input clk;
|
||||||
|
input rst;
|
||||||
|
input load;
|
||||||
|
input save;
|
||||||
|
input [31:0] address;
|
||||||
|
input [63:0] in0;
|
||||||
|
input [63:0] in1;
|
||||||
|
input [63:0] in2;
|
||||||
|
input [63:0] in3;
|
||||||
|
output reg [63:0] out0;
|
||||||
|
output reg [63:0] out1;
|
||||||
|
output reg [63:0] out2;
|
||||||
|
output reg [63:0] out3;
|
||||||
|
|
||||||
|
reg [WORD_WIDTH-1:0] mem [0:WORD_COUNT];
|
||||||
|
|
||||||
|
integer i;
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
for (i=0; i<WORD_COUNT; i=i+1) mem[i] = {WORD_WIDTH{1'b0}};
|
||||||
|
out0 = {64{1'b0}};
|
||||||
|
out1 = {64{1'b0}};
|
||||||
|
out2 = {64{1'b0}};
|
||||||
|
out3 = {64{1'b0}};
|
||||||
|
end
|
||||||
|
|
||||||
|
generate
|
||||||
|
if (WORD_WIDTH < 64) begin
|
||||||
|
always @ (address or rst or load) begin
|
||||||
|
if (load && !rst)
|
||||||
|
out0 = {{(64-WORD_WIDTH){1'b0}}, mem[address][WORD_WIDTH-1:0]};
|
||||||
|
else
|
||||||
|
out0 = {64{1'b0}};
|
||||||
|
out1 = {64{1'b0}};
|
||||||
|
out2 = {64{1'b0}};
|
||||||
|
out3 = {64{1'b0}};
|
||||||
|
end
|
||||||
|
always @ (negedge clk) begin
|
||||||
|
if (rst)
|
||||||
|
for (i=0; i<WORD_COUNT; i=i+1) mem[i] = {WORD_WIDTH{1'b0}};
|
||||||
|
else if (save)
|
||||||
|
mem[address] = in0[WORD_WIDTH-1:0];
|
||||||
|
end
|
||||||
|
end else if (WORD_WIDTH == 64) begin
|
||||||
|
always @ (address or rst or load) begin
|
||||||
|
if (load && !rst)
|
||||||
|
out0 = mem[address][63:0];
|
||||||
|
else
|
||||||
|
out0 = {64{1'b0}};
|
||||||
|
out1 = {WORD_WIDTH{1'b0}};
|
||||||
|
out2 = {WORD_WIDTH{1'b0}};
|
||||||
|
out3 = {WORD_WIDTH{1'b0}};
|
||||||
|
end
|
||||||
|
always @ (negedge clk) begin
|
||||||
|
if (rst)
|
||||||
|
for (i=0; i<WORD_COUNT; i=i+1) mem[i] = {WORD_WIDTH{1'b0}};
|
||||||
|
else if (save)
|
||||||
|
mem[address][63:0] <= in0;
|
||||||
|
end
|
||||||
|
end else if (WORD_WIDTH == 128) begin
|
||||||
|
always @ (address or rst or load) begin
|
||||||
|
if (load && !rst) begin
|
||||||
|
out0 = mem[address][63:0];
|
||||||
|
out1 = mem[address][127:64];
|
||||||
|
end else begin
|
||||||
|
out0 = {WORD_WIDTH{1'b0}};
|
||||||
|
out1 = {WORD_WIDTH{1'b0}};
|
||||||
|
end
|
||||||
|
out2 = {WORD_WIDTH{1'b0}};
|
||||||
|
out3 = {WORD_WIDTH{1'b0}};
|
||||||
|
end
|
||||||
|
always @ (negedge clk) begin
|
||||||
|
if (rst)
|
||||||
|
for (i=0; i<WORD_COUNT; i=i+1) mem[i] = {WORD_WIDTH{1'b0}};
|
||||||
|
else if (save) begin
|
||||||
|
mem[address][63:0] <= in0;
|
||||||
|
mem[address][127:64] <= in1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end else if (WORD_WIDTH == 256) begin
|
||||||
|
always @ (address or rst or load) begin
|
||||||
|
if (load && !rst) begin
|
||||||
|
out0 = mem[address][63:0];
|
||||||
|
out1 = mem[address][127:64];
|
||||||
|
out2 = mem[address][191:128];
|
||||||
|
out3 = mem[address][255:192];
|
||||||
|
end else begin
|
||||||
|
out0 = {WORD_WIDTH{1'b0}};
|
||||||
|
out1 = {WORD_WIDTH{1'b0}};
|
||||||
|
out2 = {WORD_WIDTH{1'b0}};
|
||||||
|
out3 = {WORD_WIDTH{1'b0}};
|
||||||
|
end
|
||||||
|
end
|
||||||
|
always @ (negedge clk) begin
|
||||||
|
if (rst)
|
||||||
|
for (i=0; i<WORD_COUNT; i=i+1) mem[i] = {WORD_WIDTH{1'b0}};
|
||||||
|
else if (save) begin
|
||||||
|
mem[address][63:0] = in0;
|
||||||
|
mem[address][127:64] = in1;
|
||||||
|
mem[address][191:128] = in2;
|
||||||
|
mem[address][255:192] = in3;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end endgenerate
|
||||||
|
endmodule
|
||||||
33
src/verilog/builtin_components/TC_Register.v
Normal file
33
src/verilog/builtin_components/TC_Register.v
Normal file
@@ -0,0 +1,33 @@
|
|||||||
|
module TC_Register (clk, rst, load, save, in, out);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
parameter BIT_WIDTH = 1;
|
||||||
|
input clk;
|
||||||
|
input rst;
|
||||||
|
input load;
|
||||||
|
input save;
|
||||||
|
input [BIT_WIDTH-1:0] in;
|
||||||
|
output reg [BIT_WIDTH-1:0] out;
|
||||||
|
|
||||||
|
reg [BIT_WIDTH-1:0] value;
|
||||||
|
reg reset;
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
out = {BIT_WIDTH{1'b0}};
|
||||||
|
value = {BIT_WIDTH{1'b0}};
|
||||||
|
end
|
||||||
|
|
||||||
|
always @ (negedge load or posedge load) begin
|
||||||
|
if (load)
|
||||||
|
out <= value;
|
||||||
|
else
|
||||||
|
out <= {BIT_WIDTH{1'b0}};
|
||||||
|
reset <= rst;
|
||||||
|
end
|
||||||
|
always @ (negedge clk) begin
|
||||||
|
if (reset)
|
||||||
|
value <= {BIT_WIDTH{1'b0}};
|
||||||
|
else if (save)
|
||||||
|
value <= in;
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
10
src/verilog/builtin_components/TC_Rol.v
Normal file
10
src/verilog/builtin_components/TC_Rol.v
Normal file
@@ -0,0 +1,10 @@
|
|||||||
|
module TC_Rol (in, shift, out);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
parameter BIT_WIDTH = 8;
|
||||||
|
input [BIT_WIDTH-1:0] in;
|
||||||
|
input [7:0] shift;
|
||||||
|
output [BIT_WIDTH-1:0] out;
|
||||||
|
|
||||||
|
assign out = (in >> shift) | (in << (BIT_WIDTH - shift));
|
||||||
|
endmodule
|
||||||
10
src/verilog/builtin_components/TC_Ror.v
Normal file
10
src/verilog/builtin_components/TC_Ror.v
Normal file
@@ -0,0 +1,10 @@
|
|||||||
|
module TC_Ror (in, shift, out);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
parameter BIT_WIDTH = 8;
|
||||||
|
input [BIT_WIDTH-1:0] in;
|
||||||
|
input [7:0] shift;
|
||||||
|
output [BIT_WIDTH-1:0] out;
|
||||||
|
|
||||||
|
assign out = (in << shift) | (in >> (BIT_WIDTH - shift));
|
||||||
|
endmodule
|
||||||
10
src/verilog/builtin_components/TC_Shl.v
Normal file
10
src/verilog/builtin_components/TC_Shl.v
Normal file
@@ -0,0 +1,10 @@
|
|||||||
|
module TC_Shl (in, shift, out);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
parameter BIT_WIDTH = 1;
|
||||||
|
input [BIT_WIDTH-1:0] in;
|
||||||
|
input [7:0] shift;
|
||||||
|
output [BIT_WIDTH-1:0] out;
|
||||||
|
|
||||||
|
assign out = in << shift;
|
||||||
|
endmodule
|
||||||
10
src/verilog/builtin_components/TC_Shr.v
Normal file
10
src/verilog/builtin_components/TC_Shr.v
Normal file
@@ -0,0 +1,10 @@
|
|||||||
|
module TC_Shr (in, shift, out);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
parameter BIT_WIDTH = 1;
|
||||||
|
input [BIT_WIDTH-1:0] in;
|
||||||
|
input [7:0] shift;
|
||||||
|
output [BIT_WIDTH-1:0] out;
|
||||||
|
|
||||||
|
assign out = in >> shift;
|
||||||
|
endmodule
|
||||||
9
src/verilog/builtin_components/TC_Splitter16.v
Normal file
9
src/verilog/builtin_components/TC_Splitter16.v
Normal file
@@ -0,0 +1,9 @@
|
|||||||
|
module TC_Splitter16 (in, out0, out1);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
input [15:0] in;
|
||||||
|
output [7:0] out0;
|
||||||
|
output [7:0] out1;
|
||||||
|
|
||||||
|
assign {out1, out0} = in;
|
||||||
|
endmodule
|
||||||
15
src/verilog/builtin_components/TC_Splitter8.v
Normal file
15
src/verilog/builtin_components/TC_Splitter8.v
Normal file
@@ -0,0 +1,15 @@
|
|||||||
|
module TC_Splitter8 (in, out0, out1, out2, out3, out4, out5, out6, out7);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
input [7:0] in;
|
||||||
|
output out0;
|
||||||
|
output out1;
|
||||||
|
output out2;
|
||||||
|
output out3;
|
||||||
|
output out4;
|
||||||
|
output out5;
|
||||||
|
output out6;
|
||||||
|
output out7;
|
||||||
|
|
||||||
|
assign {out7, out6, out5, out4, out3, out2, out1, out0} = in;
|
||||||
|
endmodule
|
||||||
17
src/verilog/builtin_components/TC_Switch.v
Normal file
17
src/verilog/builtin_components/TC_Switch.v
Normal file
@@ -0,0 +1,17 @@
|
|||||||
|
module TC_Switch(en, in, out);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
parameter BIT_WIDTH = 1;
|
||||||
|
input en;
|
||||||
|
input [BIT_WIDTH-1:0] in;
|
||||||
|
output [BIT_WIDTH-1:0] out;
|
||||||
|
reg [BIT_WIDTH-1:0] outval;
|
||||||
|
|
||||||
|
always @ (en or in) begin
|
||||||
|
case(en)
|
||||||
|
1'b0 : outval = {BIT_WIDTH{1'b0}};
|
||||||
|
1'b1 : outval = in;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
assign out = outval;
|
||||||
|
endmodule
|
||||||
10
src/verilog/builtin_components/TC_Xnor.v
Normal file
10
src/verilog/builtin_components/TC_Xnor.v
Normal file
@@ -0,0 +1,10 @@
|
|||||||
|
module TC_Xnor(in0, in1, out);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
parameter BIT_WIDTH = 1;
|
||||||
|
input [BIT_WIDTH-1:0] in0;
|
||||||
|
input [BIT_WIDTH-1:0] in1;
|
||||||
|
output [BIT_WIDTH-1:0] out;
|
||||||
|
|
||||||
|
assign out = in0 ~^ in1;
|
||||||
|
endmodule
|
||||||
10
src/verilog/builtin_components/TC_Xor.v
Normal file
10
src/verilog/builtin_components/TC_Xor.v
Normal file
@@ -0,0 +1,10 @@
|
|||||||
|
module TC_Xor(in0, in1, out);
|
||||||
|
parameter UUID = 0;
|
||||||
|
parameter NAME = "";
|
||||||
|
parameter BIT_WIDTH = 1;
|
||||||
|
input [BIT_WIDTH-1:0] in0;
|
||||||
|
input [BIT_WIDTH-1:0] in1;
|
||||||
|
output [BIT_WIDTH-1:0] out;
|
||||||
|
|
||||||
|
assign out = in0 ^ in1;
|
||||||
|
endmodule
|
||||||
Reference in New Issue
Block a user